公开(公告)号：US20060120444A1

公开(公告)日：2006-06-08

申请号：US11269146

申请日：2005-11-08

申请人： Sassan Tabatabaei ,  Touraj Farahmand

发明人： Sassan Tabatabaei ,  Touraj Farahmand

IPC分类号： H04B17/00

CPC分类号： H04L1/205 ,  H04B17/0085 ,  H04B17/21 ,  H04L1/08 ,  H04L1/24 ,  H04L1/244

摘要： The present subject matter relates to methodologies for providing error correction compensation to measurement systems. Data-dependant jitter may be compensated by examining both short-term and long-term bit histories after applying a predetermined synthesized calibration pattern having selected characteristics to the measurement system. Neural networks may be provided to produce error correction signals that may be applied to measured data on a bit-by-bit basis to correct jitter. The synthesized calibration sequence may correspond to a base pattern having two segments; a first segment may correspond to a copy of the base pattern while the second segment may be a copy of the base pattern with some sections inverted.

摘要翻译： 本主题涉及向测量系统提供纠错补偿的方法。 可以通过在向测量系统应用具有选定特征的预定合成校准图案之后检查短期和长期位历史来补偿依赖于数据的抖动。 可以提供神经网络以产生可以逐位地应用于测量数据以纠正抖动的纠错信号。 合成的校准序列可以对应于具有两个段的基本图案; 第一段可以对应于基本图案的副本，而第二段可以是基本图案的副本，其中一些区域被反转。

公开(公告)号：US20050286627A1

公开(公告)日：2005-12-29

申请号：US10878645

申请日：2004-06-28

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R29/26 ,  G01R31/317 ,  H03K9/08 ,  H04J11/00

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A method of estimating random jitter from measured samples of a transmitted data signal includes a first step of obtaining a plurality of measurements (e.g., pulse widths) for a plurality of selected signal edges within a transmitted data stream, where the data stream comprises a repeating data pattern having a known bit length and known number of rising edges, and wherein the time difference between adjacent measurements is determined by an event count increment equal to an integer multiple of the known number of rising edges. A time interval error value is then computed for each measured signal edge. Time interval error values are then transformed into corresponding TIE frequency components (via, for example, an FFT) for selected of the measured signal edges, wherein the TIE frequency components are representative of both noise floor as well as multiple distinct frequency peaks. Noise floor is separated from the multiple distinct frequency peaks representative of periodic jitter by replacing each TIE frequency component greater than a predetermined value with a lower predetermined replacement value. The power of the noise floor may be computed to provide an estimate of random jitter variance, from which the standard deviation may be calculated.

摘要翻译： 从所发送的数据信号的测量样本估计随机抖动的方法包括获得在所发送的数据流内的多个所选信号边缘的多个测量（例如，脉冲宽度）的第一步骤，其中数据流包括重复的 具有已知位长度和已知数量的上升沿的数据模式，并且其中相邻测量之间的时间差由等于已知数量的上升沿的整数倍的事件计数增量确定。 然后为每个测量的信号边缘计算一个时间间隔误差值。 然后，时间间隔误差值被转换成用于所选测量信号边缘的对应TIE频率分量（通过例如FFT），其中TIE频率分量代表噪声基底以及多个不同频率峰值。 通过用较低的预定替换值替换大于预定值的每个TIE频率分量，将噪声基底与代表周期性抖动的多个不同频率峰值分离。 噪声底层的功率可以被计算以提供随机抖动方差的估计，从该估计可以计算标准偏差。

公开(公告)号：US06754613B2

公开(公告)日：2004-06-22

申请号：US10244085

申请日：2002-09-16

申请人： Sassan Tabatabaei ,  Andre Ivanov

发明人： Sassan Tabatabaei ,  Andre Ivanov

IPC分类号： H03L700

CPC分类号： G04F10/00 ,  G04F10/06

摘要： A time to digital converter (TDC) has a pair of digital oscillators. The periods of the oscillators differ by T&Dgr;. The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points. A range extender circuit may be provided to extend a valid measurement range of the TDC.

摘要翻译： 数字时钟转换器（TDC）有一对数字振荡器。 振荡器的周期因TDelta而异。 振荡器由START和STOP脉冲触发。 直到由振荡器输出的信号的参考点重合为止，计数器才会计数脉冲数。 可以使用双分辨率方法进行测量。 TDC的固有抖动可以通过比较在不同点进行分辨率中的开关的测量集来确定。 可以提供范围扩展器电路来扩展TDC的有效测量范围。

公开(公告)号：US08225156B1

公开(公告)日：2012-07-17

申请号：US12954480

申请日：2010-11-24

申请人： Sassan Tabatabaei ,  Yervant Zorian

发明人： Sassan Tabatabaei ,  Yervant Zorian

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.

摘要翻译： 对于包括一些片上组件（例如，I-O，测试处理器，软封装等）的系统，提供参数测量单元（PMU）能力的外部测试单元以及执行的各种测试描述了各种方法和装置 在I-Os上通过片上测试逻辑，由外部测试单元提供的测试矢量模式。

公开(公告)号：US08032806B1

公开(公告)日：2011-10-04

申请号：US11520344

申请日：2006-09-12

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

摘要翻译： 集成电路可以至少包括指令处理器和输入输出子系统。 每个输入 - 输出子系统包括由指令处理器控制的包装电路的包装电路。 包装电路包括两个或更多个扫描寄存器，其中存储在每个扫描寄存器中的数据值可以被移出以用于分析。 封装电路还包括两个或多个更新寄存器，用于在其自身与相关联的扫描寄存器之间传送存储的数据值。 包装电路还包括耦合到扫描寄存器，更新寄存器和指令测试处理器的一组组合逻辑，其中多个I / O中的至少两个I / O，但是小于所有多个I / O 耦合到外部测试仪。

公开(公告)号：US07941287B2

公开(公告)日：2011-05-10

申请号：US12172845

申请日：2008-07-14

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R13/00

CPC分类号： G01R31/31709 ,  H04L1/205

摘要： Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

摘要翻译： 公开了用于分析周期性抖动的方法是使用连续时间间隔分析器的信号模式。 采样信号模式可以使用时间间隔误差计算来相关联，以确定采样信号数据块内的起始和停止序列，而采样同步可以基于时间间隔计算或模式间隔误差计算来实现。

公开(公告)号：US20110040509A1

公开(公告)日：2011-02-17

申请号：US12910158

申请日：2010-10-22

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G06F19/00 ,  G01K15/00

CPC分类号： G04F10/00 ,  G01R31/31922 ,  H03M1/14

摘要： The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

摘要翻译： 本主题针对高速高分辨率和精度时间插值电路。 内插器使用基本的双斜坡时间 - 数字转换器架构，但提供电路和方法来提高精度，减少有效的本征抖动并减少测量时间。 本主题的改进方面对应于引入电流镜以改善建立时间，用于改进分辨率的高频时钟和用于提高分辨率和精度的ADC采样处理。

公开(公告)号：US07853847B1

公开(公告)日：2010-12-14

申请号：US11520282

申请日：2006-09-12

申请人： Sassan Tabatabaei ,  Yervant Zorian

发明人： Sassan Tabatabaei ,  Yervant Zorian

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.

摘要翻译： 对于包括一些片上组件（例如，I-O，测试处理器，软封装等）的系统，提供参数测量单元（PMU）能力的外部测试单元以及执行的各种测试描述了各种方法和装置 在I-Os上通过片上测试逻辑，由外部测试单元提供的测试矢量模式。

公开(公告)号：US07779319B1

公开(公告)日：2010-08-17

申请号：US11520480

申请日：2006-09-12

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

摘要翻译： 集成电路可以至少包括指令处理器和输入输出子系统。 每个输入 - 输出子系统包括由指令处理器控制的包装电路的包装电路。 包装电路包括两个或更多个扫描寄存器，其中存储在每个扫描寄存器中的数据值可以被移出以用于分析。 封装电路还包括两个或多个更新寄存器，用于在其自身与相关联的扫描寄存器之间传送存储的数据值。 包装电路还包括耦合到扫描寄存器，更新寄存器和指令测试处理器的一组组合逻辑，其中多个I / O中的至少两个I / O，但是小于所有多个I / O 耦合到外部测试仪。

公开(公告)号：US07653849B1

公开(公告)日：2010-01-26

申请号：US11520200

申请日：2006-09-12

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.

摘要翻译： 集成电路可以至少包括指令处理器和输入输出子系统。 每个输入 - 输出子系统包括由指令处理器控制的包装电路的包装电路。 包装电路包括两个或更多个扫描寄存器，其中存储在每个扫描寄存器中的数据值可以被移出以用于分析。 封装电路还包括两个或多个更新寄存器，用于在其自身与相关联的扫描寄存器之间传送存储的数据值。 包装电路还包括耦合到扫描寄存器，更新寄存器和指令测试处理器的一组组合逻辑，其中多个I / O中的至少两个I / O，但是小于所有多个I / O 耦合到外部测试仪。