公开(公告)号：US08463571B2

公开(公告)日：2013-06-11

申请号：US12944892

申请日：2010-11-12

申请人： Soroush Abbaspour ,  Ayesha Akhter ,  Peter Feldmann ,  Joachim Keinert

发明人： Soroush Abbaspour ,  Ayesha Akhter ,  Peter Feldmann ,  Joachim Keinert

IPC分类号： G06F19/00 ,  G01R19/00

CPC分类号： G06F17/5036

摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.

摘要翻译： 计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。 然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅立叶变换以产生周期性电压波形的频域表示。 频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。 接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。 这允许该方法基于AC分析来计算通过每个网络的均方根电流。 然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

公开(公告)号：US08020129B2

公开(公告)日：2011-09-13

申请号：US12021723

申请日：2008-01-29

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

摘要翻译： 描述了用于对数字集成电路执行多个电压阈值时序分析的方法。 在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。 在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。 互连电路模型检索部件被配置为获得互连电路的模型。 多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。 多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。

公开(公告)号：US20110016442A1

公开(公告)日：2011-01-20

申请号：US12503924

申请日：2009-07-16

申请人： Soroush Abbaspour ,  Debjit Sinha

发明人： Soroush Abbaspour ,  Debjit Sinha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.

摘要翻译： 支持多层次级别的抽象模型被输入到分层IC芯片设计的广义静态时序分析中，以分析和优化包含多个宏抽象的芯片集成的电路的设计。 为内部抽象互连段合成的电气网络每宏执行一次，并应用于IC芯片设计中的宏抽象模型的多个实例。 合成电网是阻性电容或电阻感应电容网络或其组合。 然后使用合成的电气网络来匹配网络的脉冲响应传递函数和抽象互连段的时序模型。 该网络与连接到宏主要输出的外部互连段的电气寄生线缝合。 然后在网络拼接之前对外部互连的电寄生效应进行各种模型顺序减少。 在最终网络上执行静态时序分析。

公开(公告)号：US07814448B2

公开(公告)日：2010-10-12

申请号：US11733058

申请日：2007-04-09

申请人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Soroush Abbaspour ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.

摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

公开(公告)号：US07788617B2

公开(公告)日：2010-08-31

申请号：US12043455

申请日：2008-03-06

申请人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

发明人： Adil Bhanji ,  Soroush Abbaspour ,  Peter Feldmann ,  Debjit Sinha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.

摘要翻译： 一种精确的方法来计算电容与电容相关的引脚上的电容。 该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。 产生来自压摆和输出负载的针电容表的RC / RLC网络。 所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。 方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。

公开(公告)号：US20090193373A1

公开(公告)日：2009-07-30

申请号：US12021723

申请日：2008-01-29

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

摘要翻译： 描述了用于对数字集成电路执行多个电压阈值时序分析的方法。 在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。 在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。 互连电路模型检索部件被配置为获得互连电路的模型。 多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。 多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。

公开(公告)号：US08122411B2

公开(公告)日：2012-02-21

申请号：US12503924

申请日：2009-07-16

申请人： Soroush Abbaspour ,  Debjit Sinha

发明人： Soroush Abbaspour ,  Debjit Sinha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network.

摘要翻译： 支持多层次级别的抽象模型被输入到分层IC芯片设计的广义静态时序分析中，以分析和优化包含多个宏抽象的芯片集成的电路的设计。 为内部抽象互连段合成的电气网络每宏执行一次，并应用于IC芯片设计中的宏抽象模型的多个实例。 合成电网是阻性电容或电阻感应电容网络或其组合。 然后使用合成的电气网络来匹配网络的脉冲响应传递函数和抽象互连段的时序模型。 该网络与连接到宏主要输出的外部互连段的电气寄生线缝合。 然后在网络拼接之前对外部互连的电寄生效应进行各种模型顺序减少。 在最终网络上执行静态时序分析。

公开(公告)号：US08108815B2

公开(公告)日：2012-01-31

申请号：US12471653

申请日：2009-05-26

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

摘要翻译： 一种方法和系统，通过在给定分布的过程和环境变化源的情况下，通过执行统计时序分析检测到的定时违规来提高集成电路（IC）芯片的性能。 使用最小失真标准将分布量化为离散值。 对于IC电路的每个定时节点，使用离散值的组合的子集对定时参数执行离散的最小和最大操作。 然后离散的最小和最大运算的结果被去量化并传播到随后的定时节点及其边缘。 该过程继续，直到达到IC芯片的一个或多个主要输入和输出。 通过消除所有定时违规来修改IC芯片的设计。

公开(公告)号：US20110276933A1

公开(公告)日：2011-11-10

申请号：US12774766

申请日：2010-05-06

申请人： Revanta Banerji ,  Soroush Abbaspour ,  Peter Feldmann ,  Hemlata Gupta

发明人： Revanta Banerji ,  Soroush Abbaspour ,  Peter Feldmann ,  Hemlata Gupta

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/08 ,  G06F2217/78 ,  G06F2217/82 ,  G06F2217/84

摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.

摘要翻译： 一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性 点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。 在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。

公开(公告)号：US07941775B2

公开(公告)日：2011-05-10

申请号：US12044223

申请日：2008-03-07

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

摘要翻译： 描述了使用定时分析结果通过逻辑门执行任意波形传播的方法。 在一个实施例中，存在用于确定噪声对具有至少一个逻辑门的数字集成电路的影响的任意波形传播工具。 定时分析部件被配置为对所述至少一个逻辑门执行定时分析，并且噪声分析部件被配置为执行噪声分析。 波形传播模型合成器组件被配置为动态地合成作为时序分析的函数的波形传播模型。 波形传播模型合成器部件还被配置为施加包括噪声波形或噪声毛刺波形中的一个的任意电压波形，并且从动态合成的波形传播模型确定任意电压波形对至少一个逻辑门的影响。