公开(公告)号：US5291442A

公开(公告)日：1994-03-01

申请号：US606242

申请日：1990-10-31

申请人： Philip G. Emma ,  Joshua W. Knight ,  Kevin P. McAuliffe ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  Kevin P. McAuliffe ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0817

摘要： A system is provided for management of data in cache memories in a multiprocessor environment which allows portions of lines to be valid and exclusive, while other portions are valid, but not exclusive, or invalid. A processor may store into portions of a line under its exclusive control without invalidating copies of the line held in the cache memories of the other processors. The system includes at least two processors, a shared main memory and a system control element, and each processor has a corresponding cache memory, a modified line stack and a sectored line directory. The modified line stack identifies data lines which have been changed since being made resident in cache memory. It also identifies the status of change of each word within those lines. A "shared exclusive" flag in the system control element identifies each line for which portions of the line are under exclusive control of more than one processor. The sectored line directory identifies the control status and change status of individual words within a line flagged as "shared exclusive." If a line is shared exclusive, an entry for that line is recorded in the sectored line directory. For those lines with entries in the sectored line directory, a processor may store into words within its exclusive control, and fetch words within its exclusive or read-only control. Remote processors may fetch words which are held read-only by the local processor, and store into words which are marked invalid in the cache memory of the local processor.

摘要翻译： 提供了一种用于在多处理器环境中的高速缓冲存储器中的数据管理系统，其允许部分行有效和排他，而其他部分是有效的，但不是排他的或无效的。 处理器可以在其独占控制下存储在一部分行中，而不会使保持在其他处理器的高速缓冲存储器中的行的副本无效。 该系统包括至少两个处理器，共享主存储器和系统控制元件，并且每个处理器具有对应的高速缓冲存储器，修改的线路堆栈和扇区线路目录。 经修改的行堆栈标识自从驻留在高速缓冲存储器中以来已经改变的数据行。 它还标识了这些行中每个单词的变化状态。 系统控制元件中的“共享独占”标志标识线路的哪些部分在多于一个处理器的排他控制下的每一行。 分区线目录标识一个标记为“共享排他”的行内的单个单词的控制状态和状态。 如果一条线是共享的，该行的条目将被记录在该部分的行目录中。 对于那些在分区行目录中具有条目的行，处理器可以存储在其排他控制内的单词中，并在其独占或只读控制中取出单词。 远程处理器可以获取由本地处理器保持为只读的字，并且存储为在本地处理器的高速缓冲存储器中被标记为无效的字。

公开(公告)号：US4885680A

公开(公告)日：1989-12-05

申请号：US890428

申请日：1986-07-25

申请人： John H. Anthony ,  William C. Brantley, Jr. ,  Kevin P. McAuliffe ,  Vern A. Norton ,  Gregory F. Pfister

发明人： John H. Anthony ,  William C. Brantley, Jr. ,  Kevin P. McAuliffe ,  Vern A. Norton ,  Gregory F. Pfister

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1045 ,  G06F12/0837

摘要： A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data. When an "invalidate marked data" instruction is received, the cache controls sweep through the entire cache directory and invalidate any cache line which has the "marked data bit" set in a single pass. An extension of the invention involves using a multi-bit field rather than a single bit to provide a more versatile control of the temporary cacheability of data.

摘要翻译： 一种用于标记数据的方法和装置，该数据可临时高速缓存以便于所述数据的有效管理。 称为标记数据位（MDB）的数据的段和/或页面描述符中的一位由编译器生成，并被包含在存储器地址形式中由处理器从存储器请求数据的请求中，并存储在 在与所涉及的特定数据行相关的位置处的缓存目录。 该位在地址转换之后（在实际高速缓存的情况下）与相关联的实际地址一起被传递到高速缓存。 当缓存控件加载目录中的数据的地址时，它也将标记的数据位（MDB）存储在具有地址的目录中。 当临时可缓存数据的可缓存性从可高速缓存改变为不可缓存时，将发出单个指令以使缓存无效所有标记的数据。 当接收到“无效的标记数据”指令时，高速缓存控制扫描整个高速缓存目录，并使在一次通过中设置的“标记数据位”的任何高速缓存行无效。 本发明的扩展涉及使用多比特字段而不是单个比特来提供数据的临时高速缓存的更通用的控制。