公开(公告)号：US20120014202A1

公开(公告)日：2012-01-19

申请号：US13245856

申请日：2011-09-26

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period

Abstract translation: 在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问 与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置

公开(公告)号：US07684257B1

公开(公告)日：2010-03-23

申请号：US11958215

申请日：2007-12-17

Applicant: Christopher Lee ,  Thinh Tran ,  Joseph Tzou ,  Morgan Whately

Inventor： Christopher Lee ,  Thinh Tran ,  Joseph Tzou ,  Morgan Whately

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1006 ,  G11C11/413

Abstract: Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.

Abstract translation: 公开了一种用于在单个时钟周期时间内提供快速读取，修改和写入操作的累加存储器电路。 存储器电路被配置为以地址读取存储在存储器件中的数据。 存储器电路包括可重构加法器单元，其在单个时钟周期内产生读取，累加和写入输出。 存储器电路还被配置为最小化数据溢出。 高速累积方法包括：重置存储器电路; 从存储器电路的地址读取; 在存储器电路内执行内部加法，并在单个时钟周期内重写到存储器电路的地址。

公开(公告)号：US06526540B1

公开(公告)日：2003-02-25

申请号：US09756506

申请日：2001-01-08

Applicant: Eric Fong ,  Thinh Tran ,  Mike Teh-An Liang

Inventor： Eric Fong ,  Thinh Tran ,  Mike Teh-An Liang

IPC: G06F1750

CPC classification number: G06F17/5077 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of generating a trace library includes the steps of receiving as inputs a plurality of technology dependent parameters and a trace template and generating a trace layout from the inputs.

Abstract translation: 生成跟踪库的方法包括以下步骤：从输入中接收多个与技术相关的参数和跟踪模板并生成跟踪布局。

公开(公告)号：US10747415B2

公开(公告)日：2020-08-18

申请号：US16549859

申请日：2019-08-23

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0485 ,  G06Q50/00 ,  G06F16/9537 ,  G06F40/106 ,  H04L12/58

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US10747414B2

公开(公告)日：2020-08-18

申请号：US16300028

申请日：2017-05-10

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0485 ,  G06Q50/00 ,  G06F16/9537 ,  G06F40/106 ,  H04L12/58

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US20190377778A1

公开(公告)日：2019-12-12

申请号：US16549859

申请日：2019-08-23

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F17/21 ,  G06Q50/00 ,  G06F16/9537 ,  G06F3/0485 ,  G06Q10/10 ,  H04L29/08

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US08358557B2

公开(公告)日：2013-01-22

申请号：US13245856

申请日：2011-09-26

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period.

Abstract translation: 在相同时间段中多次访问存储器件的方法可以包括在第一次访问顺序中，与第一时钟周期的第一部分同步地开始对多个存储体之一的访问操作，并开始访问 与第一时钟周期的第二部分同步地操作到多个存储体中的另一个存储体，每个存储体具有单独的访问电路; 并且连续访问之间的时间比对于相同银行的背对背访问的访问速度更快; 其中在访问操作期间，在相同的时间段内访问每个存储体的存储位置。