公开(公告)号：US20220057915A1

公开(公告)日：2022-02-24

申请号：US17404801

申请日：2021-08-17

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F3/0481 ,  G06F3/0485 ,  G06F21/44

Abstract: An orthogonal or multi-dimensional fabric user interface is described herein. A remote server executes an operating system that provides a multi-dimensional fabric for storing content for a particular user. The user can access select content by manipulating the multi-dimensional fabric through a graphical user interface displayed on a display device. In this way, the user experiences and manipulates various data dimensions around the specific content they are accessing, rather than selecting a particular file structure location.

公开(公告)号：US08464145B2

公开(公告)日：2013-06-11

申请号：US12838035

申请日：2010-07-16

Applicant: Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

Inventor： Edward L. Grivna ,  Gabriel Li ,  Thinh Tran

IPC: G06F11/00 ,  H03M13/00

CPC classification number: G06F13/4291 ,  G06F11/1016

Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Abstract translation: 串行接口设备包括多个串行链路连接，其至少在不同的串行链路连接上接收地址值和至少一个错误检测码（EDC），从至少地址值生成的EDC，地址值的串行链路连接以及 EDC彼此分开操作; 和多个输出串行链路，输出串行链路中的至少第一个输出从对应于地址值的存储器位置读取的数据值，以及至少第二个输出串行链路，与第一个输出串行链路不同，并且与第一个串行链路分开运行 为从内存位置读取的数据值生成的EDC值。

公开(公告)号：US08149643B2

公开(公告)日：2012-04-03

申请号：US12288984

申请日：2008-10-23

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

Abstract translation: 存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

公开(公告)号：US08095747B2

公开(公告)日：2012-01-10

申请号：US12239532

申请日：2008-09-26

Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

公开(公告)号：US20100103762A1

公开(公告)日：2010-04-29

申请号：US12288984

申请日：2008-10-23

Applicant: Joseph Tzou ,  Thinh Tran ,  Jun Li

Inventor： Joseph Tzou ,  Thinh Tran ,  Jun Li

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C8/12

Abstract: A memory device and method may include separating alternating read and write accesses to different banks of a memory device.

Abstract translation: 存储器件和方法可以包括将交替的读和写访问分离到存储器件的不同组。

公开(公告)号：US20100082861A1

公开(公告)日：2010-04-01

申请号：US12239532

申请日：2008-09-26

Applicant: Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

Inventor： Bruce Barbara ,  Gabriel Li ,  Thinh Tran ,  Joseph Tzou

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F13/28

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract translation: 在一个实施例中，装置包括被配置为控制第一和第二存储器组件的存储器控​​制器。 配置为在存储器控制器和存储器组件之间传递数据的点对点数据总线可以包括从每个存储器组件到存储器控制器的直接连接。 配置为在存储器控制器和存储器组件之间传递命令的菊花链地址总线可以包括从第一存储器组件到存储器控制器的直接连接以及从第一存储器组件到第二存储器组件的菊花链连接。

公开(公告)号：US20190147017A1

公开(公告)日：2019-05-16

申请号：US16300028

申请日：2017-05-10

Applicant: Thinh Tran

Inventor： Thinh Tran

IPC: G06F17/21 ,  G06F16/9537 ,  G06Q10/10 ,  H04L29/08 ,  G06F3/0485

Abstract: A fluid timeline social network is provided herein. The fluid timeline social network includes a story database, an image database and a fluid timeline social network application, hosted at least partially on a server computer including a processor and a computer-readable storage medium. The fluid timeline social network application is configured to receive from a user computer device a created story, the created story including at least one of textual information and image information; receive from the user computer device a user-specified date to be associated with the created story; associate the created story with the user-specified date; associate the created story with an actual time and date that the created story is received by the fluid timeline social network application; and provide the story to the story database for storage.

公开(公告)号：US08675434B1

公开(公告)日：2014-03-18

申请号：US13459206

申请日：2012-04-29

Applicant: Morgan Whately ,  Thinh Tran

Inventor： Morgan Whately ,  Thinh Tran

IPC: G11C7/00

CPC classification number: G11C11/419 ,  G11C7/1042 ,  G11C7/22

Abstract: A memory device can include first sense amplifiers coupled to bit lines of a memory array in a first access period and de-coupled from the bit lines in a first sense period, the first sense amplifiers configured to amplify data signals from the memory array in the first sense period; and second sense amplifiers coupled to the bit lines in a second access period that follows the first access period and configured to amplify data signals from the memory cell array in a second sense period that overlaps the first sense period.

Abstract translation: 存储器件可以包括在第一访问周期中耦合到存储器阵列的位线的第一读出放大器，并且在第一读出周期中从位线去耦合，第一读出放大器被配置为放大来自存储器阵列中的数据信号 第一感觉期; 以及第二读出放大器，其在与所述第一访问周期之后的第二访问周期中耦合到所述位线，并且被配置为在与所述第一感测周期重叠的第二感测周期中放大来自所述存储单元阵列的数据信号。

公开(公告)号：US20090160475A1

公开(公告)日：2009-06-25

申请号：US12004131

申请日：2007-12-20

Applicant: Anwar Ali ,  Thinh Tran ,  Wilson Choi

Inventor： Anwar Ali ,  Thinh Tran ,  Wilson Choi

IPC: G01R31/26 ,  G06F17/50

CPC classification number: G01R31/2884 ,  G06F2217/40 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225

Abstract: An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.

Abstract translation: 一种用于减少芯片封装中的封装引脚数量的装置和方法，其必须用于测试目的。 在一个实施例中，本发明通过将测试球容纳在包装球阵列的减排中心来实现。 测试球用于在与印刷电路板（PWB）/印刷电路板（PCB）连接之前测试芯片封装。 测试完成后，当芯片封装连接到PWB / PCB时，测试球可能会被电隔离和未连接。 在另一个实施例中，测试球位于包装球阵列中的先前未使用的间隙位置。

公开(公告)号：US07196925B1

公开(公告)日：2007-03-27

申请号：US10927583

申请日：2004-08-26

Applicant: Joseph Tzou ,  Jithender Majjiga ,  Morgan Whately ,  Thinh Tran

Inventor： Joseph Tzou ,  Jithender Majjiga ,  Morgan Whately ,  Thinh Tran

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an α-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.

Abstract translation: 存储器设备可以包括一组存储器单元，其可以被布置在通过第一单元电源节点（106-0至106-m）接收电力的列（100）中。 电流限制器（110）可以位于第一单元电源节点（106-0至106-m）和电源（VH）之间，并将电流（限制）限制为小于闭锁保持电流（lhold_lu） 用于存储单元组（100）。 在诸如α粒子撞击的粒子事件中，限流器（110）可以防止闩锁保持电流（lhold_lu）发展，从而防止发生闩锁。 限流器（110）可以包括p沟道晶体管和/或电阻器，因此消耗存储器件的相对小的面积。