公开(公告)号：US11099994B2

公开(公告)日：2021-08-24

申请号：US17066650

申请日：2020-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David Pierson ,  Daniel Wu ,  Kai Chirca

IPC: G06F12/084 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

公开(公告)号：US10990529B2

公开(公告)日：2021-04-27

申请号：US16601881

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Wu ,  Kai Chirca ,  Matthew David Pierson

IPC: G06F12/0875 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.