公开(公告)号：US08716808B2

公开(公告)日：2014-05-06

申请号：US13861585

申请日：2013-04-12

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: H01L27/092

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract translation: 一种集成电路，其包括在存储单元阵列内具有周期性深阱结构的互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）。 深阱结构与存储单元阵列中相同导电类型（例如，n型）的表面阱区域接触，形成存储单元阵列区域中的n型和p型半导体材料的二维栅格 。 偏置导体可以接触网格以施加期望的阱偏置电压，例如在与存储单元阵列相邻的连接区域或外围电路中。

公开(公告)号：US20130320458A1

公开(公告)日：2013-12-05

申请号：US13861585

申请日：2013-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract translation: 一种集成电路，其包括在存储单元阵列内具有周期性深阱结构的互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）。 深阱结构与存储单元阵列中相同导电类型（例如，n型）的表面阱区域接触，形成存储单元阵列区域中的n型和p型半导体材料的二维栅格 。 偏置导体可以接触网格以施加期望的阱偏置电压，例如在与存储单元阵列相邻的连接区域或外围电路中。