公开(公告)号：US20210304824A1

公开(公告)日：2021-09-30

申请号：US17219092

申请日：2021-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yunchen Qiu ,  David Joseph Toops

IPC: G11C16/26

Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

公开(公告)号：US20180068713A1

公开(公告)日：2018-03-08

申请号：US15799874

申请日：2017-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C29/50 ,  G11C11/419 ,  G11C29/00

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US20130044536A1

公开(公告)日：2013-02-21

申请号：US13655512

申请日：2012-10-19

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

IPC: G11C11/00

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G11C5/025 ,  Y02P90/265

Abstract: An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.

Abstract translation: 一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。 确定在各种水平上引起邻近效应的距离。 这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。

公开(公告)号：US09576643B2

公开(公告)日：2017-02-21

申请号：US14814785

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract translation: 用于对容易受到晶体管特性的晶体管特性偏移的晶体管的操作时间筛选互补金属氧化物半导体CMOS集成电路的方法，诸如包括CMOS静态随机存取存储器（SRAM）单元的集成电路。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，可以将单独的接地电压电平施加到驱动器晶体管的源节点，或者可以将单独的电源电压电平施加到负载晶体管的源节点（或两者 ）。 以这种方式施加到晶体管的不对称偏置电压将降低晶体管驱动电流，并且因此可以模拟偏置温度不稳定性（BTI）的影响。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US20140126277A1

公开(公告)日：2014-05-08

申请号：US14151313

申请日：2014-01-09

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/41 ,  G11C29/022

Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

Abstract translation: 公开了具有缓冲读位元的SRAM（图1-6）。 集成电路包括多个存储单元（102）。 每个存储单元具有多个晶体管（200,202）。 第一存储器单元（图2）被布置为响应于有效写入字线（WWL）存储数据信号，并且响应于有源读取字线（RWL）产生数据信号。 形成在集成电路上的测试电路（104）可操作以测试第一存储单元的多个晶体管中每个晶体管的电流和电压特性（图7-10）。

公开(公告)号：US20130176772A1

公开(公告)日：2013-07-11

申请号：US13723639

申请日：2012-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yang Yi ,  Wah Kit Loh

IPC: G11C29/50

CPC classification number: G11C5/147 ,  G11C11/41 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/40 ,  G11C29/50004 ,  G11C2029/0401

Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Abstract translation: 公开了一种测试包括多个存储器阵列实例的大规模集成电路的方法以及用于辅助这种测试的集成电路结构。 在一个实施例中，通过提取布局参数和随后的电路模拟来确定阵列偏置导体中的寄生电阻引起的电压降，其导出每个存储器阵列操作期间那些导体中的电压降。 在另一个实施例中，来自每个存储器阵列的感测线选择性地连接到集成电路的测试感测端子，在该测试检测端子处外部测量每个存储器阵列处的阵列偏置电压。 可以进行施加电压的反馈控制以达到期望的阵列偏置电压。

公开(公告)号：US20130064007A1

公开(公告)日：2013-03-14

申请号：US13671281

申请日：2012-11-07

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.

Abstract translation: 固态存储器，其中每个存储器单元包括交叉点可寻址写入元件。 每个存储单元包括诸如一对交叉耦合的反相器的存储元件和用于将存储节点中的一个耦合到用于包含单元的列的读位线的读缓冲器。 每个存储单元的写元件包括由包含单元的行的写字线控制的一对或一对写选择晶体管，以及连接到相应存储节点并与写选择晶体管串联连接的写通晶体管。 写通道晶体管由包含单元的列的写位线选通。 在操作中，取决于由该列的互补写位线承载的数据状态，写参考被耦合到所选列和所选行中的存储单元的存储节点之一。

公开(公告)号：US11495301B2

公开(公告)日：2022-11-08

申请号：US17219092

申请日：2021-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yunchen Qiu ,  David Joseph Toops

IPC: G11C7/00 ,  G11C16/26

Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

公开(公告)号：US11355182B2

公开(公告)日：2022-06-07

申请号：US15799874

申请日：2017-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US09412437B2

公开(公告)日：2016-08-09

申请号：US14151313

申请日：2014-01-09

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419 ,  G11C8/16 ,  G11C29/02 ,  G11C11/41

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/41 ,  G11C29/022

Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

Abstract translation: 公开了具有缓冲读位元的SRAM（图1-6）。 集成电路包括多个存储单元（102）。 每个存储单元具有多个晶体管（200,202）。 第一存储器单元（图2）被布置为响应于有效写入字线（WWL）存储数据信号，并且响应于有源读取字线（RWL）产生数据信号。 形成在集成电路上的测试电路（104）可操作以测试第一存储单元的多个晶体管中每个晶体管的电流和电压特性（图7-10）。