公开(公告)号：US08472229B2

公开(公告)日：2013-06-25

申请号：US13655512

申请日：2012-10-19

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

IPC: G11C5/02 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G11C5/025 ,  Y02P90/265

Abstract: An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.

Abstract translation: 一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。 确定在各种水平上引起邻近效应的距离。 这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。