公开(公告)号：US06725297B1

公开(公告)日：2004-04-20

申请号：US10093146

申请日：2002-03-07

申请人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

发明人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

摘要翻译： 用于计算机系统的I / O节点的外围接口电路。 一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

公开(公告)号：US6081864A

公开(公告)日：2000-06-27

申请号：US161108

申请日：1998-09-25

申请人： Mike Lowe ,  Paul Berndt ,  Tahsin Askar ,  Enrique Rendon

发明人： Mike Lowe ,  Paul Berndt ,  Tahsin Askar ,  Enrique Rendon

IPC分类号： G06F11/267 ,  G06F13/40 ,  G06F17/50 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F11/221 ,  G06F17/5022

摘要： A system and method for dynamic verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design is created. A test configuration for the simulated model is selected through a configuration interpretation mechanism, based on a plurality of user-supplied parameters. The user-supplied parameters, for example, include the amount of the memory in the system, the number of memory banks, addresses of various PCI devices, the type of the CPU etc. The test configuration is then compiled. At run-time, the test configuration is simulated. The responses by the simulated model of the HDL design to various test stimuli from a stimulus file are then evaluated under the chosen test configuration. One or more different test configurations may be simulated at run-time, and the stimulated model's responses to a pre-determined set of test stimuli may be reevaluated for each such test configuration. Thus, the test configuration is effectively separated from the test stimulus generation mechanism. This allows permutations of a given test suite across many test configurations without creating extremely large number of tests.

摘要翻译： 公开了一种用于动态验证计算机系统组件的HDL（硬件描述语言）设计的功能的系统和方法。 创建了HDL设计的模拟模型。 基于多个用户提供的参数，通过配置解释机制来选择模拟模型的测试配置。 例如，用户提供的参数包括系统中的存储器数量，存储体的数量，各种PCI设备的地址，CPU的类型等等。然后对测试配置进行编译。 在运行时，模拟测试配置。 然后在所选择的测试配置下对HDL设计的模拟模型对刺激文件的各种测试刺激的响应进行评估。 可以在运行时模拟一个或多个不同的测试配置，并且可以针对每个这样的测试配置重新评估受刺激模型对预定的一组测试刺激的响应。 因此，测试配置与测试刺激产生机制有效分离。 这允许给定测试套件在许多测试配置中进行排列，而不会产生极大数量的测试。