公开(公告)号：US20180301409A1

公开(公告)日：2018-10-18

申请号：US16006120

申请日：2018-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Yu-Chieh LIAO ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/522 ,  H01L23/485 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

公开(公告)号：US20170213790A1

公开(公告)日：2017-07-27

申请号：US15007532

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chih WANG ,  Carlos H. DIAZ ,  Tien-Lu LIN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/228

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first conductive plug and a second conductive plug over the semiconductor substrate and adjacent to each other. The semiconductor device structure includes a first conductive via structure and a second conductive via structure over the semiconductor substrate and adjacent to each other. A first distance between the first conductive plug and the second conductive plug is less than a second distance between the first conductive via structure and the second conductive via structure. A first height of the first conductive plug is greater than a second height of the first conductive via structure.

公开(公告)号：US20150380323A1

公开(公告)日：2015-12-31

申请号：US14320181

申请日：2014-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Chih-Shen YANG ,  Tien-Lu LIN

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/306

CPC classification number: H01L21/67086 ,  H01L21/31111 ,  H01L21/67253

Abstract: A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride.

Abstract translation: 提供晶片蚀刻装置和控制晶片的蚀刻槽的方法。 晶片蚀刻装置包括蚀刻槽，其包括蚀刻槽，连接到蚀刻槽的蚀刻槽循环系统，连接到蚀刻槽的实时监视器（RTM）系统，以及与RTM系统耦合的控制系统和蚀刻 浴循环系统。 晶片蚀刻装置和用于控制晶片的蚀刻槽的方法都控制蚀刻槽中的硅酸盐浓度以稳定相对于氧化硅和氮化硅的蚀刻选择性。