公开(公告)号：US20180122739A1

公开(公告)日：2018-05-03

申请号：US15855795

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hua CHEN ,  Tai-I YANG ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.

公开(公告)号：US20180033730A1

公开(公告)日：2018-02-01

申请号：US15728762

申请日：2017-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Fang CHENG ,  Chi-Lin TENG ,  Hai-Ching CHEN ,  Hsin-Yen HUANG ,  Tien-I BAO ,  Jung-Hsun TSAI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

公开(公告)号：US20170373056A1

公开(公告)日：2017-12-28

申请号：US15701218

申请日：2017-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chewn-Pu JOU ,  Tien-I BAO

IPC: H01L27/06 ,  H01L21/02 ,  H01L23/528 ,  H01L49/02 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/31111 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM capacitor has a first electrode, a second electrode, and a high-k capacitor dielectric material disposed therebetween. The dielectric constant of the capacitor dielectric material is greater than the dielectric constant of interlayer dielectric (ILD) material. After ILD is removed from between the vertically-oriented, interdigitated portions of the first and second electrodes, a capacitor dielectric material having a dielectric constant greater than the MD dielectric material is disposed therebetween.

公开(公告)号：US20170263548A1

公开(公告)日：2017-09-14

申请号：US15065310

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hua CHEN ,  Tai-I YANG ,  Cheng-Chi CHUANG ,  Chia-Tien WU ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion.

公开(公告)号：US20140355929A1

公开(公告)日：2014-12-04

申请号：US13905404

申请日：2013-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chun-Hao TSENG ,  Ying-Hao KUO ,  Hai-Ching CHEN ,  Tien-I BAO

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/43

Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.

Abstract translation: 提供形成波导结构的实施例。 波导结构包括基板，并且基板具有互连区域和波导区域。 波导结构还包括形成在衬底中的沟槽，并且沟槽具有倾斜的侧壁表面和基本平坦的底部。 波导结构还包括形成在基板上的底部包层，并且底部包层从互连区域延伸到波导区域，并且底部包层用作互连区域中的绝缘层。 波导结构还包括在倾斜侧壁表面上形成在底部包层上的金属层。

公开(公告)号：US20130228927A1

公开(公告)日：2013-09-05

申请号：US13868140

申请日：2013-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua YU ,  Hai-Ching CHEN ,  Tien-I BAO

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

Abstract translation: 半导体结构包括在衬底上的第一电介质层。 至少一个第一导电结构在第一介电层内。 第一导电结构包括在第一介电层的顶表面上方延伸的盖部分。 至少一个第一电介质间隔物位于第一导电结构的帽部分的至少一个侧壁上。

公开(公告)号：US20180301409A1

公开(公告)日：2018-10-18

申请号：US16006120

申请日：2018-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Yu-Chieh LIAO ,  Tien-Lu LIN ,  Tien-I BAO

IPC: H01L23/522 ,  H01L23/485 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first dielectric layer over the semiconductor substrate. The semiconductor device structure includes a first conductive line embedded in the first dielectric layer. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive line. The semiconductor device structure includes a second conductive line over the second dielectric layer. The second dielectric layer is between the first conductive line and the second conductive line. The semiconductor device structure includes conductive pillars passing through the second dielectric layer to electrically connect the first conductive line to the second conductive line. The conductive pillars are spaced apart from each other.

公开(公告)号：US20190164848A1

公开(公告)日：2019-05-30

申请号：US16047115

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Pin CHUNG ,  Chih-Tang PENG ,  Tien-I BAO

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L27/092

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a first insulation material layer in a portion of a trench between a first protruding structure and a second protruding structure over a substrate and performing a pre-treatment process on the first insulation material layer. The method further includes performing a first insulation material conversion process on the first insulation material layer and forming a second insulation material layer covering the first insulation material layer in the trench. In addition, a first distance between upper portions of the first protruding structure and the second protruding structure before performing the first insulation material conversion process is different from a second distance between the upper portions of the first protruding structure and the second protruding structure after performing the first insulation material conversion process.

公开(公告)号：US20190164748A1

公开(公告)日：2019-05-30

申请号：US15944627

申请日：2018-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Cheng CHOU ,  Li Chun TE ,  Po-Cheng SHIH ,  Tien-I BAO

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  C23C16/30

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

公开(公告)号：US20190019753A1

公开(公告)日：2019-01-17

申请号：US16124567

申请日：2018-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Tien-I BAO ,  Tien-Lu LIN ,  Wei-Chen CHU

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphehe layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.