公开(公告)号：US20220278223A1

公开(公告)日：2022-09-01

申请号：US17745853

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the buffer layer, a gate electrode on the p-type semiconductor layer, a source electrode and a drain electrode adjacent to two sides of the gate electrode on the barrier layer, a hard mask on the barrier layer and around the p-type semiconductor layer, the source electrode, and the drain electrode, and a passivation layer on the hard mask.

公开(公告)号：US11367779B2

公开(公告)日：2022-06-21

申请号：US16666414

申请日：2019-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20210175343A1

公开(公告)日：2021-06-10

申请号：US16731058

申请日：2019-12-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US20210098601A1

公开(公告)日：2021-04-01

申请号：US16666430

申请日：2019-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/308

Abstract: According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US10910386B2

公开(公告)日：2021-02-02

申请号：US15943721

申请日：2018-04-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Hung-Lin Shih ,  Che-Hung Huang ,  Ping-Cheng Hsu ,  Hsu-Yang Wang

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.

公开(公告)号：US20160172190A1

公开(公告)日：2016-06-16

申请号：US14571249

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Lin Shih ,  Chueh-Yang Liu ,  Shao-Wei Wang ,  Che-Hung Huang ,  Po-Hua Jen ,  Shih-Hao Su

IPC: H01L21/02 ,  H01L21/283

CPC classification number: H01L21/28211 ,  H01L21/76224 ,  H01L21/823462

Abstract: A gate oxide formation process includes the following steps. A first gate oxide layer is formed on a substrate. The first gate oxide layer is thinned to a first predetermined thickness. The first gate oxide layer is then thickened to a second predetermined thickness, to thereby form a second gate oxide layer.

Abstract translation: 栅极氧化物形成工艺包括以下步骤。 在基板上形成第一栅氧化层。 第一栅极氧化物层被薄化到第一预定厚度。 然后将第一栅极氧化物层增厚至第二预定厚度，从而形成第二栅极氧化物层。