公开(公告)号：US09006058B1

公开(公告)日：2015-04-14

申请号：US14150489

申请日：2014-01-08

Applicant: United Microelectronics Corp.

Inventor： Tung-Ming Chen ,  Yu-Chun Huang ,  Shin-Chuan Huang ,  Chia-Jong Liu ,  I-Fang Huang

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is described. A semiconductor substrate is provided, wherein the substrate has a first area and a second area. A first gate structure and a second gate structure are formed over the substrate in the first area and the substrate in the second area, respectively. A first spacer is framed on the sidewall of each gate structure. At least one etching process including at least one wet etching process is performed. The first spacer is removed. A second spacer is formed on the sidewall of each gate structure. A mask layer is formed in the second area. Ion implantation is formed using the mask layer, the first gate structure and the second spacer as a mask to form S/D extensions in the substrate beside the first gate structure in the first area. The mask layer is then removed.

Abstract translation: 对半导体装置的制造方法进行说明。 提供一种半导体衬底，其中衬底具有第一区域和第二区域。 第一栅极结构和第二栅极结构分别在第一区域和第二区域中的衬底上形成在衬底上。 第一间隔件框架在每个栅极结构的侧壁上。 执行包括至少一个湿蚀刻工艺的至少一个蚀刻工艺。 第一个垫片被去除。 在每个栅极结构的侧壁上形成第二间隔物。 在第二区域中形成掩模层。 使用掩模层，第一栅极结构和第二间隔物作为掩模形成离子注入，以在第一区域中的第一栅极结构旁边的衬底中形成S / D延伸。 然后去除掩模层。

公开(公告)号：US20240014310A1

公开(公告)日：2024-01-11

申请号：US18371440

申请日：2023-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20230378314A1

公开(公告)日：2023-11-23

申请号：US18221404

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/7783 ,  H01L29/2003

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US11749740B2

公开(公告)日：2023-09-05

申请号：US16731058

申请日：2019-12-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US11489048B2

公开(公告)日：2022-11-01

申请号：US17337415

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/78 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

公开(公告)号：US20210288149A1

公开(公告)日：2021-09-16

申请号：US17337415

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66

Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

公开(公告)号：US11063124B2

公开(公告)日：2021-07-13

申请号：US16691616

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: A high-electron mobility transistor includes a substrate; a buffer layer over the substrate; a GaN channel layer over the buffer layer; a AlGaN layer over the GaN channel layer; a gate recess in the AlGaN layer; a source region and a drain region on opposite sides of the gate recess; a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively; and a p-GaN gate layer in and on the gate recess.

公开(公告)号：US11935947B2

公开(公告)日：2024-03-19

申请号：US16596738

申请日：2019-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/7787

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

公开(公告)号：US20230369448A1

公开(公告)日：2023-11-16

申请号：US18221396

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/7783 ,  H01L29/2003

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US11804544B2

公开(公告)日：2023-10-31

申请号：US17575655

申请日：2022-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/265 ,  H01L29/205 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/7786 ,  H01L21/26546 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66462 ,  H01L21/2654 ,  H01L21/28264 ,  H01L29/41766 ,  H01L29/4236

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.