公开(公告)号：US20060181302A1

公开(公告)日：2006-08-17

申请号：US11055852

申请日：2005-02-11

申请人： Daniel Dreps ,  John Schief ,  Glen Wiedemeier ,  Joel Ziegelbein

发明人： Daniel Dreps ,  John Schief ,  Glen Wiedemeier ,  Joel Ziegelbein

IPC分类号： H03K17/16

CPC分类号： H03K17/164

摘要： The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while slower slew rates may be implemented in the communication channels when crosstalk is more of a concern.

公开(公告)号：US20060095620A1

公开(公告)日：2006-05-04

申请号：US10977884

申请日：2004-10-29

申请人： Daniel Dreps ,  Frank Ferriaolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

发明人： Daniel Dreps ,  Frank Ferriaolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

IPC分类号： G06F12/14 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G06F13/1689

摘要： A method for re-driving data in a memory subsystem. The method includes receiving controller interface signals and a forwarded interface clock associated with the controller interface signals at a memory module. The memory module is part of a cascaded interconnect system. The controller interface signals are sampled with the forwarded interface clock and the sampling results in the controller interface signals being latched into interface latches. The controller interface signals are then latched into local latches using a local clock on the memory module. The contents of the local latches along with the local clock are transmitted to an other memory module or controller in the cascaded interconnect system.

摘要翻译： 一种用于重新驱动存储器子系统中的数据的方法。 该方法包括在存储器模块处接收控制器接口信号和与控制器接口信号相关联的转发接口时钟。 存储器模块是级联互连系统的一部分。 控制器接口信号采用转发的接口时钟进行采样，并将控制器接口信号中的采样结果锁存到接口锁存器中。 然后，使用存储器模块上的本地时钟将控制器接口信号锁存到本地锁存器中。 本地锁存器与本地时钟一起发送到级联互连系统中的另一个存储器模块或控制器。

公开(公告)号：US20060023482A1

公开(公告)日：2006-02-02

申请号：US10903371

申请日：2004-07-30

申请人： Daniel Dreps ,  Frank Ferriaolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

发明人： Daniel Dreps ,  Frank Ferriaolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

IPC分类号： G11C5/06

CPC分类号： G11C5/04

摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。