公开(公告)号：US08093657B2

公开(公告)日：2012-01-10

申请号：US12181007

申请日：2008-07-28

申请人： Roy Childs Flaker ,  Catherine O'Brien, legal representative ,  Scott Flaker, legal representative ,  Shirley A. Flaker, legal representative ,  Bruce Flaker, legal representative ,  Anne Flaker, legal representative ,  Heather Flaker, legal representative ,  Louis C. Hsu ,  Jente Kuang

发明人： Roy Childs Flaker ,  Louis C. Hsu ,  Jente Kuang

IPC分类号： H01L27/13

CPC分类号： G11C16/08 ,  H01L27/1203

摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.

摘要翻译： 根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。 在本发明的优选实施例中，提供了一种脉冲放电电路。 这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。 如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。 利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。 或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。 这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。 利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。 各个器件的整体体电阻对器件的电位影响最小。

公开(公告)号：US20060290384A1

公开(公告)日：2006-12-28

申请号：US11168717

申请日：2005-06-28

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FET device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FET device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

摘要翻译： 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 逻辑树具有堆叠配置，其具有至少一个多栅极FET器件，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点 时钟信号的相位。 多栅极FET器件具有耦合到第一逻辑输入的一个栅极和耦合到用于预充电动态节点的时钟信号的补码的第二栅极。

公开(公告)号：US20060290383A1

公开(公告)日：2006-12-28

申请号：US11168692

申请日：2005-06-28

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

摘要翻译： 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。