公开(公告)号：US20240363173A1

公开(公告)日：2024-10-31

申请号：US18768091

申请日：2024-07-10

申请人： Intel NDTM US LLC

发明人： Narayanan RAMANAN

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

摘要： Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

公开(公告)号：US20240363168A1

公开(公告)日：2024-10-31

申请号：US18230336

申请日：2023-08-04

申请人： Western Digital Technologies, Inc.

发明人： Abhijith Prakash ,  Xiang Yang

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

摘要： The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.

公开(公告)号：US12131789B2

公开(公告)日：2024-10-29

申请号：US17847545

申请日：2022-06-23

申请人： Samsung Electronics Co., Ltd.

发明人： Junho Kim ,  Jinyoung Kim ,  Sehwan Park ,  Seoyoung Lee ,  Jisang Lee ,  Joonsuc Jang

IPC分类号： G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

摘要： Aggressor memory cells connected to one or more aggressor wordlines are grouped into aggressor cell groups by performing a read operation with respect to the aggressor wordlines based on one or more grouping read voltages, where the aggressor wordlines are adjacent to a selected wordline corresponding to a read address among wordlines of a memory block. Selected memory cells connected to the selected wordline are grouped into a selected cell groups respectively corresponding to the aggressor cell groups. Group read conditions respectively corresponding to the selected cell groups are determined and group read operations are performed with respect to the plurality of selected cell groups based on the group read conditions. The read errors are reduced by grouping the selected memory cells into the selected cell groups according to the change of operation environments.

公开(公告)号：US12125545B2

公开(公告)日：2024-10-22

申请号：US17689182

申请日：2022-03-08

申请人： Kioxia Corporation

发明人： Reiko Sumi ,  Takashi Maeda ,  Hidehiro Shiga

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/08

摘要： A semiconductor memory device includes a driver that, in a write operation, applies a first voltage to a first select gate line, applies a second voltage lower than the first voltage to a second select gate line, applies a third voltage equal to or higher than the first voltage to a first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to a second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to a first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to a second dummy word line on a lowermost layer.

公开(公告)号：US12125538B2

公开(公告)日：2024-10-22

申请号：US17834024

申请日：2022-06-07

申请人： Samsung Electronics Co., Ltd.

发明人： Won-bo Shim ,  Ji-ho Cho ,  Yong-seok Kim ,  Byoung-taek Kim ,  Sun-gyung Hwang

IPC分类号： G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L29/788 ,  G06F3/06 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C16/3459 ,  H01L29/7885 ,  G06F3/0679 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

摘要： A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

公开(公告)号：US20240347113A1

公开(公告)日：2024-10-17

申请号：US18752870

申请日：2024-06-25

申请人： KIOXIA CORPORATION

发明人： Yasuhiro SHIINO ,  Eietsu TAKAHASHI ,  Koki UENO

IPC分类号： G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3427 ,  G11C16/349

摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

公开(公告)号：US20240339167A1

公开(公告)日：2024-10-10

申请号：US18748097

申请日：2024-06-20

申请人： SK hynix Inc.

发明人： Jeong Ho JEON

IPC分类号： G11C29/08 ,  G11C16/04 ,  G11C16/08

CPC分类号： G11C29/08 ,  G11C16/0483 ,  G11C16/08

摘要： A method of operating a host device according to the present technology includes determining an area to be tested among a mapped area and an unmapped area included in a storage area of a storage device, generating a test request corresponding to the determined area, and transmitting the generated test request to the storage device.

公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC分类号： G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

摘要： Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US12112806B2

公开(公告)日：2024-10-08

申请号：US18205149

申请日：2023-06-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yo-Han Lee

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/24 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/27 ,  H10B43/27

摘要： In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively. A boosting operation is performed to boost voltages of channels of the plurality of stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block. Program voltage disturbance and pass voltage disturbance are reduced through control of the switching operation of the intermediate switching transistors.

公开(公告)号：US12112802B2

公开(公告)日：2024-10-08

申请号：US17974271

申请日：2022-10-26

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhihong Li ,  Jing Wei ,  Masao Kuriyama

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

摘要： The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.