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65 条记录 (耗时 0.029 秒)

    Low-loss transmission line TDM communication link and system
    22.
    发明授权
    Low-loss transmission line TDM communication link and system 有权
    低损耗传输线TDM通信链路和系统

    公开(公告)号：US09087157B2

    公开(公告)日：2015-07-21

    申请号：US13405335

    申请日：2012-02-26

    申请人： William Loh ,  Erik Vaclav Chmelar

    发明人： William Loh ,  Erik Vaclav Chmelar

    IPC分类号： H04B1/38 ,  G06F13/38

    CPC分类号： G06F13/38 ,  G06F13/4291 ,  G06F2213/0038

    摘要： A time division multiplexing intra-chip communication system comprising at least one communication link. Such communication link comprises serialization and transmission circuitry, reception and deserialization circuitry, and at least one coaxial or wafer-level package transmission line interconnect therebetween. Such coaxial or wafer-level package transmission line interconnect may carry signals from such transmit circuitry to such receive circuitry. Such intra-chip communication links may achieve single-cycle operation or multi-cycle operation. Single single-cycle operation may be conducive to synchronous FSM design methodologies while multi-cycle operation may be conducive to data transfers to and from memory.

    摘要翻译： 一种时分复用片上通信系统，包括至少一个通信链路。 这种通信链路包括串行化和传输电路，接收和反序列化电路以及它们之间的至少一个同轴或晶片级封装传输线互连。 这种同轴或晶片级封装传输线互连可将来自这种传输电路的信号传送到这种接收电路。 这样的片上通信链路可以实现单周期操作或多周期操作。 单个单周期操作可能有助于同步FSM设计方法，而多周期操作可能有助于从存储器传输数据。

    Circuit simulation using step response analysis in the frequency domain
    23.
    发明授权
    Circuit simulation using step response analysis in the frequency domain 有权
    电路仿真使用频域中的阶跃响应分析

    公开(公告)号：US08798981B2

    公开(公告)日：2014-08-05

    申请号：US12143895

    申请日：2008-06-23

    申请人： Choshu Ito ,  William Loh

    发明人： Choshu Ito ,  William Loh

    IPC分类号： G06G7/56 ,  G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/50 ,  G06F17/5009 ,  G06F17/5045

    摘要： A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.

    摘要翻译： 用于模拟电路对应用于电路的ESD输入激励的响应的方法包括以下步骤：将电路的描述接收到电路仿真程序中，该电路包括指示在该电路中的磁耦合的至少一个互感元件 电路 在非线性元件的各个DC偏置点处产生电路中的非线性元件的线性近似; 获得电路的频域传递函数; 获得电路的时域脉冲响应作为频域传递函数的函数; 积分时域脉冲响应以产生电路的阶跃响应，阶跃响应指示电路对ESD输入刺激的响应; 以及分析电路的阶跃响应以确定电路是否将在对应于电路的规定参数内运行。

    DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD
    24.
    发明申请
    DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD 有权
    防止CDM ESD导致功能失效的设计方法

    公开(公告)号：US20100100859A1

    公开(公告)日：2010-04-22

    申请号：US12255002

    申请日：2008-10-21

    申请人： Choshu Ito ,  Tze Wee Chen ,  William Loh

    发明人： Choshu Ito ,  Tze Wee Chen ,  William Loh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5036 ,  G06F2217/72 ,  G06F2217/82

    摘要： A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.

    摘要翻译： 一种防止CDM ESD事件引起功能故障的设计方法。 晶体管模型用于对细胞的最终状态建模，然后使用模拟器来识别不可侵入的细胞。 然后鉴定潜在的故障部位的细胞。 被识别为潜在受害者的细胞由具有相同逻辑功能的先前识别的无形细胞所取代。 另一方面，如果不能发现具有相同功能的单元，则可以在潜在的牺牲晶体管的前面插入不可变缓冲单元（不会影响逻辑功能）作为保护。 通过用已被确定为无害的细胞代替所有潜在的受害细胞，所得到的设计将被保证是CDM耐受性的。

    Circuit protection system
    25.
    发明申请
    Circuit protection system 有权
    电路保护系统

    公开(公告)号：US20070019345A1

    公开(公告)日：2007-01-25

    申请号：US11174135

    申请日：2005-06-30

    申请人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

    发明人： William Loh ,  Ken Doniger ,  Payman Zarkesh-Ha ,  Jau-Wen Chen ,  Choshu Ito

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266

    摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

    摘要翻译： 一种用于保护电路的系统和方法。 该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。 逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。 根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。 此外，保护电路保护电路免受常规FET无法保护的ESD事件。

    Bakery basket
    27.
    发明授权
    Bakery basket 失效
    面包篮

    公开(公告)号：US4982844A

    公开(公告)日：1991-01-08

    申请号：US545866

    申请日：1990-06-29

    申请人： Michael K. Madan ,  Vinod Malhotra ,  William Loh

    发明人： Michael K. Madan ,  Vinod Malhotra ,  William Loh

    IPC分类号： B65D21/06

    CPC分类号： B65D21/06

    摘要： A bakery basket includes a bottom, opposed side walls and a back wall joined together to form an upwardly open basket body. The side walls include a plurality of vertical support towers which are formed of an outwardly directed projection which defines a hollow opening on the interior of the basket. A slidable bail is positioned within the side walls on a horizontal support ledge therein. Each slidable bail includes one or more support lugs, such as an upper support lug and a lower support lug, and open areas adjacent each hollow opening in the side walls. Slidable bails are moveable in a variety of positions, including positioning the open areas aligned with the hollow openings, positioning the lower support lugs aligned with the hollow openings and positioning the upper support lugs aligned with the hollow openings. In this manner, the baskets may be stacked at one or more height levels and may also be nested together, depending on the position of the slidable bails.

    摘要翻译： 面包店篮子包括底部相对的侧壁和连接在一起以形成向上打开的篮状物的后壁。 侧壁包括多个垂直支撑塔，其由向外指向的突出部形成，该突出部限定了篮子内部上的中空开口。 可滑动的吊环位于其中的水平支撑壁架的侧壁内。 每个可滑动的吊环包括一个或多个支撑凸耳，例如上支撑凸耳和下支撑凸耳，以及与侧壁中的每个中空开口相邻的敞开区域。 可滑动的围兜可以在各种位置上移动，包括将敞开的区域定位成与中空开口对准，将下支撑突起定位成与中空开口对齐并且将上支撑突出部定位成与中空开口对齐。 以这种方式，篮子可以以一个或多个高度水平层叠，并且还可以嵌套在一起，这取决于可滑动的小腿的位置。

    Chemical tobacco sucker control
    28.
    发明授权
    Chemical tobacco sucker control 失效
    化学烟草吸盘控制

    公开(公告)号：US4828601A

    公开(公告)日：1989-05-09

    申请号：US101324

    申请日：1987-09-25

    申请人： William Loh ,  Pawan K. Bassi

    发明人： William Loh ,  Pawan K. Bassi

    IPC分类号： A01N43/18 ,  C07D409/12

    CPC分类号： C07D409/12 ,  A01N43/18

    摘要： Methods and compositions for controlling tobacco suckers, which comprise administering an effective amount of certain 2-[1-[(5-chlorothien-2-yl)methoxyimino]ethyl]-3-hydroxy or alkanoyloxy-5-(tetrahydro-2H-thiopyran-3-yl)cyclohex-2-en-1-one derivatives to said tobacco plants or their growth medium.

    摘要翻译： 用于控制烟草吸盘的方法和组合物，其包括施用有效量的某些2- [1 - [（5-氯噻吩-2-基）甲氧基亚氨基]乙基] -3-羟基或烷酰氧基-5-（四氢-2H-噻喃） -3-基）环己-2-烯-1-酮衍生物加入到所述烟草植物或其生长培养基中。

    Row Based Analog Standard Cell Layout Design and Methodology
    30.
    发明申请
    Row Based Analog Standard Cell Layout Design and Methodology 有权
    基于行的模拟标准单元布局设计和方法

    公开(公告)号：US20130042216A1

    公开(公告)日：2013-02-14

    申请号：US13572697

    申请日：2012-08-13

    申请人： William Loh ,  Erik Vaclav Chmelar

    发明人： William Loh ,  Erik Vaclav Chmelar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5063

    摘要： A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.

    摘要翻译： 一种设计SoC的物理布局的系统和方法，该SoC包括将高度限制在预定行高度或整数倍的模拟标准单元的基于行的放置。 模拟标准单元库可以被ECAD工具利用，以类似于这样的ECAD工具可以利用数字标准单元库来映射，放置和路由数字地图，放置和路由数字地图，放置和路由模拟和混合信号电路 电路。 数字，模拟和混合信号电路的映射，放置和布线可以在统一的ECAD SoC物理设计流程中进行。 最后，教授了通用型模拟标准单元，以进一步提高模拟和混合信号SoC布局的速度和效率。