公开(公告)号：US09235660B1

公开(公告)日：2016-01-12

申请号：US14243506

申请日：2014-04-02

Applicant: Xilinx, Inc.

Inventor： Ruibing Lu ,  Sabyasachi Das ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/505 ,  G06F2217/62

Abstract: In an approach for processing a circuit design by a programmed processor, a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC) is input. A critical path is determined from a first sequential element to a second sequential element assigned to the placed circuit design. A first clock buffer that provides a clock signal to the first and second sequential elements is determined, and an unused clock buffer is selected based on proximity to the first sequential element. The circuit design is modified to include the unused clock buffer as a second clock buffer coupled to receive a clock signal in parallel with the first clock buffer and to provide a clock signal to the first sequential element.

Abstract translation: 在通过编程处理器处理电路设计的方法中，输入放置在可编程集成电路（IC）的可编程资源上的放置电路设计。 从第一顺序元件确定关键路径到分配给放置的电路设计的第二顺序元件。 确定向第一和第二顺序元件提供时钟信号的第一时钟缓冲器，并且基于与第一顺序元件的接近度来选择未使用的时钟缓冲器。 电路设计被修改为将未使用的时钟缓冲器包括为第二时钟缓冲器，其耦合以接收与第一时钟缓冲器并行的时钟信号，并向第一顺序元件提供时钟信号。