公开(公告)号：US20050150462A1

公开(公告)日：2005-07-14

申请号：US11030808

申请日：2005-01-05

申请人： Jung-Hun Seo ,  Yun-Ho Choi ,  Young-Wook Park ,  Jeong-Tae Kim

发明人： Jung-Hun Seo ,  Yun-Ho Choi ,  Young-Wook Park ,  Jeong-Tae Kim

IPC分类号： H01L21/205 ,  C23C16/00 ,  C23C16/44 ,  C23C16/458 ,  H01L21/687

CPC分类号： C23C16/4586 ,  C23C16/4404 ,  C23C16/4581 ,  H01L21/68742 ,  Y10T29/49

摘要： Provided are a lift pin capable of preventing aluminum from depositing on the lift pin when depositing a metallic layer on a wafer through chemical vapor deposition. a system using the lift pin, and a method of manufacturing the same. The lift pin is made of stainless steel and is oxidized at a predetermined temperature for a predetermined time, such that the lift pin is not deposited with aluminum during a CVD process. Since the CVD vacuum processing chamber utilizes the heater and the lift pin which are made of oxidized SUS material, aluminum does not deposit on the heater and the lift. Therefore, when the lift pin is lowered, the lift pin is not lowered by its own weight, thereby preventing a wafer from being broken. Also, the lift pin is prevented from being ruptured by a robot moving in and out of an opening of the CVD vacuum processing chamber.

摘要翻译： 提供了一种提升销，其能够通过化学气相沉积在金属层上沉积金属层时能够防止铝沉积在升降销上。 使用升降销的系统及其制造方法。 提升销由不锈钢制成，并在预定温度下氧化预定时间，使得在CVD工艺期间提升销不被铝沉积。 由于CVD真空处理室利用由氧化的SUS材料制成的加热器和提升销，铝不会沉积在加热器和电梯上。 因此，当升降销降低时，提升销不会因其自重而下降，从而防止晶片破裂。 此外，防止升降销被机械人移入和移出CVD真空处理室的开口而破裂。

公开(公告)号：US5982704A

公开(公告)日：1999-11-09

申请号：US4995

申请日：1998-01-09

申请人： Jeong-Tae Kim

发明人： Jeong-Tae Kim

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C8/18 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A row address strobe signal input buffer and method for converting an external input row address strobe signal to an internal signal and protecting the internal signal from background noise in the circuit. In the preferred embodiment the invention level-shifts the row address strobe signal to an internal signal of CMOS signal level. It then latches the internal signal to its current state and opens a transmission gate cutting off the internal signal from the external row address strobe signal. This prevents glitches in the internal signal due to noise in the circuit introduced due to the external row address strobe signal being of a TTL level. The gate remains open for a delayed period of time, the delay determined by a delay circuit or by the length of a pulse from a pulse generator. After the delay period, the gate is closed, restoring the signal connection between the external row address signal and the internal signal.

摘要翻译： 行地址选通信号输入缓冲器和用于将外部输入行地址选通信号转换为内部信号并保护内部信号免受电路背景噪声的方法。 在优选实施例中，本发明将行地址选通信号电平移位到CMOS信号电平的内部信号。 然后将内部信号锁存到其当前状态，并打开传输门，从外部行地址选通信号切断内部信号。 这防止由于外部行地址选通信号为TTL电平而引入的电路中的噪声导致内部信号的毛刺。 门保持断开延迟时间，由延迟电路确定的延迟或来自脉冲发生器的脉冲长度。 在延迟时间之后，门关闭，恢复外部行地址信号和内部信号之间的信号连接。

公开(公告)号：US5915130A

公开(公告)日：1999-06-22

申请号：US921617

申请日：1997-09-02

申请人： Jeong-Tae Kim

发明人： Jeong-Tae Kim

IPC分类号： G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  H04N5/00 ,  H04N5/225 ,  G06F13/00

CPC分类号： H04L12/40117 ,  G06F13/4291

摘要： A digital interface apparatus operable to transmit and receive non-compressed digital data can allow a data interface between digital image apparatuses such as a digital VCR and a digital camcorder and a computer. A transmission timing controller in the digital interface apparatus for transmitting and receiving digital data via an IEEE 1394 serial bus, generates a clock select signal and timing signals. A transmission memory records data to be transmitted in synchronization with the clock designated by the clock select signal according to the timing signals generated by the transmission timing controller and outputs the recorded data in synchronization with a third clock. A controller generates the third clock, adds additional information to the data output from the transmission memory to then be transmitted via the IEEE 1394 serial bus, receives data transmitted via the IEEE 1394 serial bus, and restores a frame signal from the information added in the received data. A reception timing controller generates the clock select signal and timing signals. A reception memory records data output from the controller in synchronization with the third clock supplied from the controller according to timing signals generated by the reception timing controller, and outputs the recorded data in synchronization with the clock designated by the clock select signal generated by the reception timing controller.

摘要翻译： 可操作以发送和接收非压缩数字数据的数字接口装置可以允许诸如数字VCR和数字摄录机的数字图像设备与计算机之间的数据接口。 用于通过IEEE 1394串行总线发送和接收数字数据的数字接口装置中的发送定时控制器产生时钟选择信号和定时信号。 发送存储器根据由发送定时控制器生成的定时信号与由时钟选择信号指定的时钟同步地记录要发送的数据，并与第三时钟同步地输出记录数据。 控制器产生第三时钟，将附加信息添加到从传输存储器输出的数据，然后通过IEEE 1394串行总线发送，接收通过IEEE 1394串行总线发送的数据，并从添加的信息中恢复帧信号 收到的资料。 接收定时控制器产生时钟选择信号和定时信号。 接收存储器根据由接收定时控制器产生的定时信号，与从控制器提供的第三时钟同步地记录从控制器输出的数据，并且与由接收器生成的时钟选择信号指定的时钟同步地输出记录数据 定时控制器