公开(公告)号：US20130127801A1

公开(公告)日：2013-05-23

申请号：US13610900

申请日：2012-09-12

Applicant: Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

Inventor： Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

IPC: G06F3/038

CPC classification number: G09G3/20 ,  G09G2310/0218 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2310/0297

Abstract: A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Abstract translation: 显示面板包括安装在显示面板的第一侧的多个第一驱动开关，安装在显示面板的第二侧的多个第二开关，多个第一数据线，多个第二数据线， 多个扫描线，以及多个像素。 每个第一驱动开关包括第一输入端和多个第一输出端。 每个第二驱动开关包括第二输入端和多个第二输出端。 第一数据线电连接到第一输出端。 第二数据线电连接到第二输出端。 多个像素电连接到多个第一数据线，第二数据线和用于显示图像的扫描线。 第一数据线和第二数据线被交错布置。

公开(公告)号：US20080246042A1

公开(公告)日：2008-10-09

申请号：US11902229

申请日：2007-09-20

Applicant: Yu-Hsin Ting

Inventor： Yu-Hsin Ting

IPC: H01L33/00 ,  H01L21/441

CPC classification number: G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3265

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract translation: 提供了包括至少一个晶体管，第一存储电容器，第一导电层，层间介电层，第二导电层，钝化层和第三导电层的像素结构。 第一存储电容器电连接到晶体管。 具有至少一个第一开口的层间绝缘层覆盖第一导电层。 第二导电层形成在层间电介质层的一部分上，并通过第一开口与第一导电层电连接。 具有至少一个第二开口的钝化层覆盖晶体管和第二导电层。 第三导电层形成在钝化层的一部分上，并通过第二开口与晶体管电连接。 第一存储电容器由第三导电层，钝化层和第二导电层形成。

公开(公告)号：US20060158409A1

公开(公告)日：2006-07-20

申请号：US11332922

申请日：2006-01-17

Applicant: Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

Inventor： Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2310/0248

Abstract: A driving circuit. The driving circuit includes a plurality of scan shift register cells, a pair of complementary clock signal lines, and a horizontal start signal generator. Each scan shift register cell comprises a bidirectional circuit, a shift register coupled to the bidirectional circuit, a transmission gate coupled to the shift register, and a data line coupled to the transmission gate. The complementary clock signal lines are coupled to the shift registers. The horizontal start signal generator provides a horizontal start signal to the bidirectional circuits in the first and a subsequent scan shift register cells. The shift register in each scan shift register cell provides an output signal to the bidirectional circuit in the next scan shift register cell. The bidirectional circuit in each scan shift register cell also receives the output signal from the shift register in the next scan shift register cell.

Abstract translation: 驱动电路。 驱动电路包括多个扫描移位寄存器单元，一对互补时钟信号线和水平启动信号发生器。 每个扫描移位寄存器单元包括双向电路，耦合到双向电路的移位寄存器，耦合到移位寄存器的传输门，以及耦合到传输门的数据线。 互补时钟信号线耦合到移位寄存器。 水平启动信号发生器向第一和随后的扫描移位寄存器单元中的双向电路提供水平启动信号。 每个扫描移位寄存器单元中的移位寄存器向下一个扫描移位寄存器单元中的双向电路提供输出信号。 每个扫描移位寄存器单元中的双向电路还从下一个扫描移位寄存器单元中的移位寄存器接收输出信号。

公开(公告)号：US08836679B2

公开(公告)日：2014-09-16

申请号：US13567582

申请日：2012-08-06

Applicant: Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

Inventor： Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3685 ,  G09G2310/0297

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract translation: 一方面，LCD包括具有M条扫描线和N条数据线的像素矩阵的显示面板和多路复用器馈通补偿电路，其包括用于提供P视频信号的P信号线，P多路复用器和K对 提供K对控制信号的控制线。 每个复用器电耦合到对应的信号线并且具有K个信道。 每个通道包括并联在信号线和相应的数据线之间的第一和第二开关，用于选择性地将视频信号传输到对应的数据线。 每对控制线分别电耦合到每个多路复用器的相应通道的第一和第二开关。 每对控制信号被配置为使得关闭第一和第二开关中的一个的时间早于关闭另一个开关的时间。

公开(公告)号：US08724406B2

公开(公告)日：2014-05-13

申请号：US13524070

申请日：2012-06-15

Applicant: Chien-Chang Tseng ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting

Inventor： Chien-Chang Tseng ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting

IPC: G11C7/00

CPC classification number: G09G3/3677 ,  G09G2310/0286

Abstract: A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.

Abstract translation: 双向移位寄存器包括第一寄存器电路和第二寄存器电路。 第一寄存器电路包括第一寄存器级和具有n个扫描信号输出端的第一输出缓冲级。 第一寄存器级电耦合到第三电压源。 第一输出缓冲级电耦合到第二电压源和第一电压源。 第二寄存器电路具有与第一寄存器电路相似的电路结构; 其中第一寄存器电路和第二寄存器电路各使用n + 1个时钟信号线，并且n是正整数。

公开(公告)号：US20130173870A1

公开(公告)日：2013-07-04

申请号：US13524070

申请日：2012-06-15

Applicant: Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting

Inventor： Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting

IPC: G06F12/00

CPC classification number: G09G3/3677 ,  G09G2310/0286

Abstract: A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.

Abstract translation: 双向移位寄存器包括第一寄存器电路和第二寄存器电路。 第一寄存器电路包括第一寄存器级和具有n个扫描信号输出端的第一输出缓冲级。 第一寄存器级电耦合到第三电压源。 第一输出缓冲级电耦合到第二电压源和第一电压源。 第二寄存器电路具有与第一寄存器电路相似的电路结构; 其中第一寄存器电路和第二寄存器电路各使用n + 1个时钟信号线，并且n是正整数。

公开(公告)号：US20120146962A1

公开(公告)日：2012-06-14

申请号：US13087328

申请日：2011-04-14

Applicant: Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

Inventor： Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2320/0214

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract translation: 有源液晶显示面板包括像素阵列，栅极驱动电路，数据驱动电路和模拟缓冲器。 栅极驱动电路用于驱动M是自然数的M个第一扫描线。 模拟缓冲器耦合到栅极驱动电路，并包括M个缓冲电路和调节器。 每个缓冲电路根据M个第一扫描线的对应的第一扫描线的输出信号驱动相应的第二扫描线，并且调节器用于保持提供给M个缓冲电路的至少一个参考电压。

公开(公告)号：US20120104402A1

公开(公告)日：2012-05-03

申请号：US12938867

申请日：2010-11-03

Applicant: Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: In one aspect of the invention, an analog buffer circuit includes a p-channel field effect transistor (PTFT) and an n-channel field effect transistor (NTFT). Each of the PTFT and NTFT has a source region and a drain region defining a channel region therebetween, formed on a substrate such that the drain regions of the PTFT and the NTFT are in substantial contact with each other, a gate layer formed over and insulated from the corresponding channel region, a source electrode insulated from the gate layer and electrically connected to the corresponding source region, and a common drain electrode insulated from the gate layer and the source electrode, and is electrically connected to the drain regions of both the PTFT and the NTFT through a via defined over the depletion region.

Abstract translation: 在本发明的一个方面，模拟缓冲电路包括p沟道场效应晶体管（PTFT）和n沟道场效应晶体管（NTFT）。 PTFT和NTFT中的每一个具有形成在基板上的源极区域和限定其间的沟道区域的漏极区域，使得PTFT和NTFT的漏极区域彼此基本接触;形成在绝缘层上的栅极层 从相应的沟道区域，与栅极层绝缘并电连接到对应的源极区域的源极电极和与栅极层和源极电极绝缘的公共漏电极，并且电连接到两个PTFT的漏极区域 和通过在耗尽区域上定义的通孔的NTFT。

公开(公告)号：US07745825B2

公开(公告)日：2010-06-29

申请号：US11902229

申请日：2007-09-20

Applicant: Yu-Hsin Ting

Inventor： Yu-Hsin Ting

IPC: H01L29/04

CPC classification number: G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3265

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract translation: 提供了包括至少一个晶体管，第一存储电容器，第一导电层，层间介电层，第二导电层，钝化层和第三导电层的像素结构。 第一存储电容器电连接到晶体管。 具有至少一个第一开口的层间绝缘层覆盖第一导电层。 第二导电层形成在层间电介质层的一部分上，并通过第一开口与第一导电层电连接。 具有至少一个第二开口的钝化层覆盖晶体管和第二导电层。 第三导电层形成在钝化层的一部分上，并通过第二开口与晶体管电连接。 第一存储电容器由第三导电层，钝化层和第二导电层形成。