公开(公告)号：US20050171988A1

公开(公告)日：2005-08-04

申请号：US10907933

申请日：2005-04-21

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/10 ,  H03H17/02 ,  H03H17/06

CPC classification number: H03H17/0219 ,  H03H17/06 ,  H03H2017/0072

Abstract: A symmetric unit filter (L10″) is designed by combining in series two unit filters (1L10, 2L10) having asymmetric numerical sequences as filter coefficients (H1 to H3 and H4 to H6). Thus, by designing a filter by series connection, it is possible to automatically obtain a desired digital filter coefficient only by combining one type of unit filter (L10″) in series. Moreover, a symmetric numerical sequence {−1, 0, 9, 16, 9, 0, −1}/32 is divided at the center into two parts and one of them is used as the asymmetric filter coefficients (H1 to H3 and H4 to H6). This reduces the number of necessary taps, eliminates use of a window function, and prevents generation of a discretization error in the filter characteristic obtained.

Abstract translation: 通过组合具有不对称数字序列的串联的两个单位滤波器（1L10,2L10）作为滤波器系数（H 1至H 3和H 4至H 6）来设计对称单元滤波器（L 10“）。 因此，通过串联连接设计滤波器，只能通过组合一种类型的单元滤波器（L10“）自动获得期望的数字滤波器系数。 此外，将对称数字序列{-1,0,9,16,9,0-1} / 32在中心分成两部分，其中一个用作不对称滤波器系数（H 1至H 3 和H 4至H 6）。 这减少了所需的抽头的数量，消除了使用窗口功能，并且防止了所获得的滤波器特性中的离散化误差的产生。

公开(公告)号：US06700521B2

公开(公告)日：2004-03-02

申请号：US10275247

申请日：2002-11-06

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M166

CPC classification number: H03H17/0657 ,  G06F1/02 ,  H03M3/508

Abstract: A digital input is 8-fold oversampled, delay circuits 11−1 to 11−4 and multipliers/adders 12 to 15 perform a convolution arithmetic while multipliers/adders 4 to 10 process the oversampling data into predetermined digital basic waveforms, and continuous interpolation values can be obtained, thereby requiring no low pass filter which causes deterioration of phase characteristics, and suppressing an interpolation abortion error by setting finite interpolating functions. Furthermore, by obtaining apart of oversampling data as input data by using an AND gate 2, a subsequent process using the digital basic waveform and the convolution arithmetic can be performed in a very simple process.

Abstract translation: 数字输入为8倍过采样，延迟电路11-1至11-4和乘法器/加法器12至15执行卷积运算，而乘法器/加法器4至10将过采样数据处理为预定数字基本波形，连续插值 从而不需要导致相位特性恶化的低通滤波器，并且通过设置有限的内插函数来抑制插值堕胎误差。 此外，通过使用与门2获得过采样数据作为输入数据，可以在非常简单的过程中执行使用数字基本波形和卷积运算的后续处理。

公开(公告)号：US06657567B2

公开(公告)日：2003-12-02

申请号：US10018096

申请日：2001-12-14

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M700

CPC classification number: H03M7/30

Abstract: There are provided: an offset adding section 3 for converting signed digital data to unsigned digital data by adding an offset value to signed digital data to be compressed, a rounding section 5 for reducing the number of bits per word by performing a rounding operation of a lower-order bit on the unsigned digital data, a timing synthesizer 6 and a compressing section 7 for sampling the digital data undergoing a rounding operation at a time interval of a point where a differential value varies in polarity and for obtaining as compressed data a pair of a discrete amplitude data value on each sample point and a timing data value indicative of a time interval between sample points. When a signal is compressed and expanded on a time base, the operation can be performed on the time base without frequency conversion.

Abstract translation: 提供：偏移加法部分3，用于通过向要压缩的带符号数字数据添加偏移值来将有符号数字数据转换为无符号数字数据;舍入部分5，用于通过执行以下操作来减少每个字的比特数： 无符号数字数据上的低位位置，定时合成器6和压缩单元7，用于以差分值极性变化的点的时间间隔对经过舍入操作的数字数据进行采样，并获得压缩数据对 在每个采样点上具有离散振幅数据值，以及指示采样点之间的时间间隔的定时数据值。 当信号在时基上被压缩和扩展时，该操作可以在时基上执行而不进行频率转换。

公开(公告)号：US06489910B1

公开(公告)日：2002-12-03

申请号：US09890517

申请日：2001-07-31

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M166

CPC classification number: H03H17/028 ,  H03M3/508

Abstract: It is object to provide an oversampling circuit and a digital-to-analog converter which have small circuit scales and component costs of which are reduced. The data input at predetermined intervals is multiplied by the multiplying section 1 by four types of multiplicators, and the multiplication results are cyclically held in data holding sections 2-1 through 2-4. The data selectors 3-1 through 3-4 sequentially read out the four types of multiplication results held in the data holding sections 2-1 through 2-4 one to one corresponding respectively to the data selectors 3-1 through 3-4 in a predetermined order, thereby outputting predetermined step functions. Each step function corresponding to each of the four pieces of data inputted sequentially is generated at a different timing, each of the integrating sections 4-1 through 4-4 performs a digitally integrating process two times on each step function, and the results are added up, thereby performing the oversampling process to give a pseudo-rise of a sampling frequency to each piece of input digital data.

Abstract translation: 目的在于提供一种过采样电路和数模转换器，其具有小的电路规模和其部件成本的降低。 以预定间隔输入的数据通过乘法器1乘以四种类型的乘法器，乘法结果循环保持在数据保持部分2-1至2-4中。 数据选择器3-1至3-4顺序地将保存在数据保持部2-1至2-4中的四种类型的相乘结果分别依次读出，分别对应于数据选择器3-1至3-4 从而输出预定的步骤功能。 在不同的定时生成与顺序输入的四个数据中的每一个相对应的每个步骤功能，每个积分部4-1至4-4对每个阶梯函数执行两次数字积分处理，并且将结果相加 从而执行过采样处理以对每个输入数字数据给出采样频率的伪上升。

公开(公告)号：US06486815B1

公开(公告)日：2002-11-26

申请号：US09890537

申请日：2001-07-31

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M166

CPC classification number: H03H17/028 ,  H03H17/0657 ,  H03M3/508

Abstract: It is object to provide an oversampling circuit and a digital to analog converter capable of realizing a smaller circuit and reducing a cost of parts. The oversampling circuit comprises multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, and two integrating circuits 5-1 and 5-2. Input data is multiplied by four multiplicators by the multiplying section 1, and four multiplication results held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of four step functions outputted from the respective data selectors, and then digital integrating operations corresponding to the sum are carried out by means of two integrating circuits.

Abstract translation: 目的是提供一种能够实现更小的电路并降低部件成本的过采样电路和数模转换器。 过采样电路包括乘法部分1，四个数据保持部分2-1至2-4，四个数据选择器3-1至3-4，加法部分4和两个积分电路5-1和5-2。 输入数据由乘法部分1乘以四个乘法器，并且在数据保持部分中保持四个相乘结果作为一组。 数据选择器以预定顺序读出保存在四个数据保持部分中的数据，并生成步骤功能数据。 加法部分将从各个数据选择器输出的四步函数的值相加，然后通过两个积分电路执行与该和相对应的数字积分运算。

公开(公告)号：US5389968A

公开(公告)日：1995-02-14

申请号：US862881

申请日：1992-04-03

Applicant: Yukio Koyanagi ,  Yuji Suwa

Inventor： Yukio Koyanagi ,  Yuji Suwa

IPC: H04N5/225 ,  H04N5/232

CPC classification number: H04N5/23203

Abstract: A CCD television camera has a head part separated from the rest of the camera. The camera head part contains a CCD imaging device and is connected by only a single line coaxial cable to a main part containing a DC power source, a line flag output circuit, and a one H-alternate switch. The coaxial cable may be up to several hundred meters in length. Respective ends of the coaxial cable are connected to the head and main parts through hydrid coils to facilitate sending of DC power current and an accurately controlled sinusoidal clock frequency signal from the main part to the camera head part, and the sending of video signals over the same single cable line from the camera head part to the main part. The hybrid coils are tuned for resonance with the clock frequency and a PLL circuit, including the coaxial cable, regulates the clock frequency to adjust for different lengths of cable.

Abstract translation: CCD电视摄像机具有与摄像机其余部分分离的头部。 相机头部包含CCD成像装置，并且仅通过单线同轴电缆连接到包含直流电源的主要部分，线路标志输出电路和一个H交替开关。 同轴电缆的长度可达数百米。 同轴电缆的两端通过环形线圈连接到头部和主要部件，以方便发送直流电源电流和精确控制的正弦时钟频率信号，从主要部分到相机头部，并通过视频信号发送视频信号 相同的单根电缆线从相机头部到主要部分。 混合线圈被调谐为与时钟频率谐振，并且PLL电路（包括同轴电缆）调节时钟频率以针对不同长度的电缆进行调整。

公开(公告)号：US07590675B2

公开(公告)日：2009-09-15

申请号：US10556775

申请日：2004-03-18

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/10

CPC classification number: H03H17/06

Abstract: An original filter is connected to an adjustment filter in the longitudinal way. The original filter has a first filter coefficient of a symmetric numeric string. The adjustment filter has a contact point at a position where the maximum value is acquired in the original filter frequency amplitude characteristic A and has a symmetric second filter coefficient realizing the frequency amplitude characteristic B having the minimum value at the contact point. By executing a convolution calculation of the first filter coefficient and the second filter coefficient, it is possible to design a desired filter coefficient.

Abstract translation: 原始过滤器以纵向方式连接到调节过滤器。 原始滤波器具有对称数字串的第一滤波器系数。 调整滤波器在原始滤波器频率幅度特性A中在获取最大值的位置处具有接触点，并且具有实现在接触点处具有最小值的频率振幅特性B的对称的第二滤波器系数。 通过执行第一滤波器系数和第二滤波器系数的卷积计算，可以设计期望的滤波器系数。

公开(公告)号：US07400676B2

公开(公告)日：2008-07-15

申请号：US10979733

申请日：2004-11-03

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03H7/40

CPC classification number: G10L19/26 ,  H03G5/005 ,  H03H17/06

Abstract: A waveform of a desired frequency characteristic is input as a numeric value string and is subjected to a reverse FFT so as to obtain a filter coefficient group. Thus, without having any expert knowledge and only by inputting a waveform of a desired frequency characteristic as an image, it is possible to easily design a first FIR filter constituting a tone quality adjustment device. Moreover, by performing a predetermined calculation on the numeric value string input and performing a reverse FFT on the result, it is possible to easily design a second FIR filter having a frequency characteristic symmetric to the first FIR filter with respect to the gain reference value as an axis.

Abstract translation: 将期望频率特性的波形作为数值串输入，并进行反向FFT，以获得滤波器系数组。 因此，没有任何专业知识，并且仅通过输入期望的频率特性的波形作为图像，可以容易地设计构成音调质量调节装置的第一FIR滤波器。 此外，通过对数值串输入进行规定的计算并对结果执行反向FFT，可以容易地设计相对于增益参考值具有与第一FIR滤波器对称的频率特性的第二FIR滤波器作为 一个轴。

公开(公告)号：US07330865B2

公开(公告)日：2008-02-12

申请号：US10708405

申请日：2004-03-01

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/10

CPC classification number: H03H17/06

Abstract: A method for designing a digital filter for outputting a signal that is the sum of the products of multiplication of the signals at the taps of delay units (11-16) by the filter factors given by factor units (21-25), several times of the signals, wherein various filters from a low-pass filter to a high-pass filter can be designed by using, as the filter factors, the terms of a symmetrical sequence, e.g., {−1, 0, 9, 16, 9, 0, −1} in which the sum of all the terms is not zero, and the sum of every other terms is equal to the sum of the other every other terms and has the same sign of that of the other every other terms and by simply changing the signs of the terms of the sequence. By applying a combination of cascade connection of filters, conversion of clock rate, and transfer of filter factors, a digital filter having desired frequency characteristics can be extremely simply designed.

Abstract translation: 一种用于输出数字滤波器的方法，用于输出作为延迟单元（11-16）的抽头上的信号乘法乘积的乘积与由因子单元（21-25）给出的滤波器因数相乘的信号的几倍 的信号，其中可以通过使用对称序列的项作为滤波因子来设计来自低通滤波器到高通滤波器的各种滤波器，例如{-1,0,9,16,9 ，0，-1}，其中所有项的总和不为零，每个其他项的总和等于其他每个其他项的总和，并且具有与其他每个其他项相同的符号， 通过简单地改变序列条款的符号。 通过应用滤波器的级联连接，时钟速率的转换和滤波器因子的传递的组合，可以非常简单地设计具有期望的频率特性的数字滤波器。

公开(公告)号：US20050289206A1

公开(公告)日：2005-12-29

申请号：US11217241

申请日：2005-09-02

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/10 ,  H03H17/06

CPC classification number: H03H17/06 ,  H03H2017/0072

Abstract: A numerical string consisting of a ratio of “−1, m, −1” or “1, m, 1” is subjected to a predetermined moving average calculation n times. A numerical string thus obtained is used as filter coefficients of a basic filter and at least one basic filter is combined in an arbitrary way for cascade connection, thereby calculating the filter coefficients of the digital filter to be obtained. This significantly reduces the number of taps and the number of multipliers used as compared to the conventional FIR filter. Moreover, by using the numerical strings “−1, m, −1” and “1, m, 1” so that the filter impulse response becomes a finite-base function, it is possible to obtain a preferable frequency characteristic having no discretization error and having a great attenuation amount out of band.

Abstract translation: 由比例“-1，m，-1”或“1，m，1”组成的数字串进行n次的预定移动平均计算。 这样获得的数字串被用作基本滤波器的滤波器系数，并且以任意方式组合至少一个基本滤波器用于级联连接，从而计算要获得的数字滤波器的滤波器系数。 与传统的FIR滤波器相比，这显着地减少了抽头的数量和乘法器的数量。 此外，通过使用数字串“-1，m，-1”和“1，m，1”，使得滤波器脉冲响应成为有限基函数，可以获得没有离散误差的优选频率特性 并具有非常大的衰减量。