公开(公告)号：US20090091585A1

公开(公告)日：2009-04-09

申请号：US12281792

申请日：2006-09-28

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G09G5/00

CPC classification number: G06T3/4007 ,  H04N1/3935 ,  H04N7/0135

Abstract: A screen enlargement and reduction device includes: a coefficient calculation unit (2) for obtaining a coefficient corresponding to a pixel value of each pixel of an original image and storing the coefficient in a coefficient RAM (4) for each interpolation position set in accordance with an enlargement and reduction ratio “s”; and a coefficient multiplication unit (6) for obtaining a pixel value of each pixel at the interpolation position by multiplying/adding a pixel value of each pixel of the original image extracted by a matrix decomposition unit (5) in accordance with a second process clock (cs2) generated by a clock generation unit (1) and a coefficient read out from the coefficient memory (4) in accordance with a first process clock (cs1). When actually performing an interpolation calculation, the device can be used only by reading out a necessary coefficient from the coefficient RAM (4). The device eliminates the need of calculating a coefficient upon interpolation calculation and the need of use of a large image memory for performing an interpolation calculation.

Abstract translation: 屏幕缩小装置包括：系数计算单元（2），用于获得与原始图像的每个像素的像素值对应的系数，并将系数存储在根据 缩小比例“s”; 以及系数乘法单元（6），用于通过将由矩阵分解单元（5）提取的原始图像的每个像素的像素值与第二处理时钟相乘，从而获得插值位置处的每个像素的像素值 （cs2），以及根据第一处理时钟（cs1）从系数存储器（4）读出的系数。 当实际执行插值计算时，只能通过从系数RAM（4）读出必要的系数来使用该装置。 该装置消除了在插值计算时计算系数的需要，并且需要使用大图像存储器来进行插值计算。

公开(公告)号：US20070053420A1

公开(公告)日：2007-03-08

申请号：US11465056

申请日：2006-08-16

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03K5/159

CPC classification number: H03H17/06 ,  H03H2017/0072

Abstract: For example, more than one FIR-type basic filters having a symmetric sequence of numbers having a predetermined characteristic as filter coefficient are combined and connected in cascade connection. The filter coefficients are calculated and for the y-bits data of the calculated filter coefficients, the lower bits are cut off for rounding so as to obtain filter coefficients of x-bits (x

Abstract translation: 例如，具有作为滤波器系数的具有预定特性的数字的对称序列的多于一个的FIR型基本滤波器被组合并且级联连接。 计算滤波器系数，并且对于计算的滤波器系数的y比特数据，将较低比特切断用于舍入，以获得x比特（x

公开(公告)号：US20060190520A1

公开(公告)日：2006-08-24

申请号：US11381091

申请日：2006-05-01

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06G7/02

CPC classification number: H03H11/04 ,  H03H17/02 ,  H03H17/026

Abstract: An analog filter includes a first arithmetic operation section 2-1 having a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a ΔΣ-modulated signal and an analog adder for adding the input and output signals of the S/H circuit, in which the number of stages of the S/H circuits 11-1, 14-1, 17-1 and 20-1 decreases toward the end of cascade connection, and a second arithmetic operation section 2-2 configured in the same way, which are cascade connected. By using such an analog filter, over-sampling and convolution of a ΔΣ-modulated signal are conducted so that the envelope of the filter output may be a quadratic curve of finite carrier that converges to zero at finite sampling points to prevent phase distortion of an LPF and a discretization error due to a conventional function. Compared with a conventional circuit for over-sampling and convolution, the number of stages of the S/H circuits and the number of adders are small.

Abstract translation: 模拟滤波器包括具有串联连接的多组处理电路的第一算术运算部分2 <1>，每个处理电路具有用于保持ΔΣ调制信号的多级S / H电路 以及模拟加法器，用于将S / H电路的输入和输出信号相加，其中S / H电路11 SUB-1，14-SUB的次数，17 和20 SUB-1 降低到级联连接的结束，并且第二算术运算部分2 相同的方式，它们是级联的。 通过使用这种模拟滤波器，进行ΔΣ调制信号的过采样和卷积，使得滤波器输出的包络可以是在有限采样点处收敛到零的有限载波的二次曲线，以防止相位失真 LPF和由于常规功能引起的离散化误差。 与用于过采样和卷积的常规电路相比，S / H电路的级数和加法器的数量小。

公开(公告)号：US06486814B2

公开(公告)日：2002-11-26

申请号：US09890519

申请日：2001-07-31

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M166

CPC classification number: H03M3/504

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises four D flip-flops 10-1 through 10-4, four multipliers 12-1 through 12-4, three adders 14-1 through 14-3, a D/A converter 16, and two integrating circuits 18-1 and 18-2. Input data is fed sequentially to the four D flip-flops and held therein. The multiplier multiplies the data held in the respective D flip-flops by different multiplicators in the first half and second half of one clock period and the multiplication results are added by the three adders. A stepwise analog voltage corresponding to the sum is generated by the D/A converter 16 and integrated twice by means of the two integrating circuits 18-1 and 18-2.

Abstract translation: 目的在于提供一种能够产生具有较小失真的输出波形的数模转换器，而不增加部件的运行速度。 AD / A转换器包括四个D触发器10-1至10-4，四个乘法器12-1至12-4，三个加法器14-1至14-3，D / A转换器16和两个积分电路18 -1和18-2。 输入数据被顺序馈送到四个D触发器并保持在其中。 乘法器在一个时钟周期的前半部分和后半部分中乘以不同的乘法器在各个D触发器中保持的数据，乘法结果由三个加法器相加。 对应于和的逐步模拟电压由D / A转换器16产生并通过两个积分电路18-1和18-2集成两次。

公开(公告)号：US20090135970A1

公开(公告)日：2009-05-28

申请号：US12063230

申请日：2006-08-09

Applicant: Hiroshi Miyagi ,  Yukio Koyanagi

Inventor： Hiroshi Miyagi ,  Yukio Koyanagi

IPC: H04L27/08

CPC classification number: H04B1/30 ,  H03G3/3052 ,  H03G3/3068 ,  H04L27/14 ,  H04L27/3836

Abstract: A direct conversion receiver wherein even when signals are continuously received, the automatic gain control can be implemented in accordance with the signal levels from which DC offset voltages have been removed. The direct conversion receiver comprises a low-noise amplifier 14, a mixer 16, a local oscillator (LO) 20, a lowpass filter (LPF) 23, a baseband amplifier (second amplifier) 24, an analog-to-digital converter (ADC) 26, digital-to-analog converters (DAC) 28, 32, a signal processing section 30, a speaker 34, a DC component extracting filter 100, an average value calculating circuit 200 and a subtractor 210. The average value calculating circuit 200 calculates an average value of the signal levels of the baseband signals. The DC offset voltage extracted by the DC component filter 100 is subtracted from the average value, thereby generating a control voltage, which then controls the gain of the input circuit 10 or low-noise amplifier 14.

Abstract translation: 一种直接转换接收机，其中即使当信号被连续接收时，可以根据已经去除了DC偏移电压的信号电平来实现自动增益控制。 直接转换接收机包括低噪声放大器14，混频器16，本地振荡器（LO）20，低通滤波器（LPF）23，基带放大器（第二放大器）24，模数转换器 ）26，数模转换器（DAC）28,32，信号处理部30，扬声器34，直流分量提取滤波器100，平均值计算电路200和减法器210.平均值计算电路200 计算基带信号的信号电平的平均值。 从平均值中减去由DC分量滤波器100提取的DC偏移电压，从而产生控制电压，控制电压然后控制输入电路10或低噪声放大器14的增益。

公开(公告)号：US20090070395A1

公开(公告)日：2009-03-12

申请号：US12281722

申请日：2007-03-05

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/17

CPC classification number: H03H17/0621 ,  G06F17/17 ,  G06T3/4007

Abstract: An interpolation function generation circuit is formed by cascade connecting a first FIR filter (10) having a numerical value string composed of a ratio “−α, α, β, β, α, −α” (α is an emphasis coefficient and β is a fixed value) as a filter coefficient and a second FIR filter (20) having a numerical value string composed of a ratio “1, 3, 5, . . . , m−1, m−1, . . . , 5, 3, 1” when the tap length is an odd number and “1, 3, 5, . . . , n−2, n−1, n−2, . . . , 5, 3, 1” if the tap length is an odd number (m and n are multiples of the oversampling). With only the two FIR filter (10, 20), it is possible to easily realize an interpolation function having a variable emphasis.

Abstract translation: 通过级联连接具有由“α，α，β，β，α，α”组成的数值串的第一FIR滤波器（10）形成插值函数产生电路（α是强调系数，β是 作为滤波器系数的固定值）和具有由比例“1,3,5 ...，m-1，m-1，...，5”组成的数值串的第二FIR滤波器（20） 3,1“，当抽头长度为奇数时，如果抽头长度为1，3，5，...，n-2，n-1，n-2，...，5，3，1 是奇数（m和n是过采样的倍数）。 仅使用两个FIR滤波器（10,20），可以容易地实现具有可变强调的插值功能。

公开(公告)号：US20080208941A1

公开(公告)日：2008-08-28

申请号：US11915085

申请日：2006-02-08

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/17

CPC classification number: H03H17/0621 ,  G06T3/4007 ,  H03H17/0223 ,  H03H17/026 ,  H03H17/0294 ,  H03H17/0657 ,  H04N7/0135

Abstract: There are included a three-tap FIR calculating part (2) that multiples data outputted from three taps on a tapped delay line by respective filter factors comprising a ratio value sequence of “−1, m, −1”; and an n-tap FIR calculating part (3) that multiples data outputted from n taps on a tapped delay line by respective filter factors comprising a predetermined value sequence. Interpolation values can be determined by use of sum-of-products calculations using various factor sequences comprising various values of m and n. The three-tap FIR calculating part (2) is adapted to determine interpolation values by use of the sum-of-products calculations that always use only three values. In this way, the circuit scale can be reduced and further the calculation process can be simplified, thereby achieving a high-rate interpolation process.

Abstract translation: 包括三抽头FIR计算部分（2），其通过包括比率值序列“-1，m，-1”的各个滤波器因数对从抽头延迟线上的三个抽头输出的数据进行倍数; 以及n抽头FIR计算部分（3），其通过包括预定值序列的各个滤波器因数对抽头延迟线上的n个抽头输出的数据进行倍数。 插值可以通过使用包含各种m和n值的各种因子序列的乘积求和计算来确定。 三抽头FIR计算部分（2）适于通过使用总是仅使用三个值的积和积计算来确定内插值。 以这种方式，可以减小电路规模，进一步简化计算处理，从而实现高速率插值处理。

公开(公告)号：US20080012882A1

公开(公告)日：2008-01-17

申请号：US11775969

申请日：2007-07-11

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G09G5/00 ,  G06F17/17

CPC classification number: H03H17/0657 ,  H03H17/06

Abstract: An over-sampling unit 2 that over-samples inputted sequential respective sample values to be N sample values and an FIR filter unit 3 that applies filter processing to the over-sampled respective sample values using coefficients formed by a sequence of numerical values (1/2N2, 3/2N2, 5/2N2, . . . , (N−3)/2N2, (N−1)/2N2, (N−1)/2N2, (N−3)/2N2, . . . , 5/2N2, 3/2N2, 1/2N2} (when N is an even number) are provided. Consequently, original discrete sample points are smoothly interpolated along a spline curve according to over-sampling and FIR filter processing and, in a frequency characteristic of an output, a pass band is limited to 2/N of a sampling frequency.

Abstract translation: 将输入的顺序各个采样值过采样为N个采样值的过采样单元2和使用由数值序列（1/1）形成的系数对过采样的各采样值进行滤波处理的FIR滤波器单元3， 2 N 2，3 / 2N 2，5 / 2N 2，...，（N-3）/ 2N 2， （N-1）/ 2N 2，（N-1）/ 2N 2，（N-1）/ 2N 2 >，...，5 / 2N 2，3 / 2N 2，1 / 2N 2（当N是偶数时） 因此，根据过采样和FIR滤波处理，沿着样条曲线平滑地插入原始离散采样点，并且在输出的频率特性中，通带被限制为采样频率的2 / N。

公开(公告)号：US20060208831A1

公开(公告)日：2006-09-21

申请号：US10556775

申请日：2004-03-18

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03H7/38

CPC classification number: H03H17/06

Abstract: An original filter is connected to an adjustment filter in the longitudinal way. The original filter has a first filter coefficient of a symmetric numeric string. The adjustment filter has a contact point at a position where the maximum value is acquired in the original filter frequency amplitude characteristic A and has a symmetric second filter coefficient realizing the frequency amplitude characteristic B having the minimum value at the contact point. By executing a convolution calculation of the first filter coefficient and the second filter coefficient, it is possible to design a desired filter coefficient.

公开(公告)号：US07085799B2

公开(公告)日：2006-08-01

申请号：US10203004

申请日：2001-12-06

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06G7/02

CPC classification number: H03H15/02

Abstract: An analog filter includes a first arithmetic operation section 2-1 having a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a ΔΣ-modulated signal and an analog adder for adding the input and output signals of the S/H circuit, in which the number of stages of the S/H circuits 11-1, 14-1, 17-1 and 20-1 decreases toward the end of cascade connection, and a second arithmetic operation section 2-2 configured in the same way, which are cascade connected. By using such an analog filter, over sampling and convolution of a ΔΣ-modulated signal are conducted so that the envelope of the filter output may be a quadratic curve of finite carrier that converges to zero at finite sampling points to prevent phase distortion of an LPF and a discretization error due to a conventional function. Compared with a conventional circuit for over-sampling and convolution, the number of stages of the S/H circuits and the number of adders are small.

Abstract translation: 模拟滤波器包括具有串联连接的多组处理电路的第一算术运算部分2 <1>，每个处理电路具有用于保持ΔΣ调制信号的多级S / H电路 以及模拟加法器，用于将S / H电路的输入和输出信号相加，其中S / H电路11 SUB-1，14-SUB的次数，17 和20 SUB-1 降低到级联连接的结束，并且第二算术运算部分2 相同的方式，它们是级联的。 通过使用这种模拟滤波器，进行DeltaSigma调制信号的过采样和卷积，使得滤波器输出的包络可以是在有限采样点收敛到零的有限载波的二次曲线，以防止LPF的相位失真 以及由常规功能引起的离散化误差。 与用于过采样和卷积的常规电路相比，S / H电路的级数和加法器的数量小。