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21.
公开(公告)号:US20170329732A1
公开(公告)日:2017-11-16
申请号:US15586798
申请日:2017-05-04
Inventor: Heiko Kalte , Dominik Lubeley
IPC: G06F13/362 , G06F13/40
CPC classification number: G06F13/3625 , G06F13/00 , G06F13/4068 , G06F17/5031 , G06F2217/84 , H04L7/0041
Abstract: Method for temporally synchronizing the output of signals and/or temporally synchronizing the processing of captured signals on a plurality of input and/or output channels of an electronic circuit, comprising the following steps: (a) combining a number of channels, in particular a proportion of all channels of the circuit, to form a logical group; (b) retrieving the channel latency of each channel belonging to the group from a data source; (c) determining the greatest channel latency from all retrieved channel latencies and at least temporarily storing the greatest channel latency as the group latency; (d) for each channel belonging to the group: determining the temporal difference between the group latency and the retrieved channel latency of the respective channel and storing the determined difference as a channel-associated latency offset in a memory, in particular a memory of the circuit; and (e) influencing the signal propagation via a respective channel on the basis of at least its respective stored latency offset.