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    FRAME SYNCH DETECTION WITH RATE ADAPTATION
    1.
    发明公开
    FRAME SYNCH DETECTION WITH RATE ADAPTATION 审中-公开

    公开(公告)号：US20240204983A1

    公开(公告)日：2024-06-20

    申请号：US18393343

    申请日：2023-12-21

    Applicant: Cypress Semiconductor Corporation

    Inventor： Claudio REY

    IPC: H04L7/033 ,  H04L7/00 ,  H04L7/04

    CPC classification number: H04L7/0331 ,  H04L7/0041 ,  H04L7/042

    Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

    TRANSPARENT CLOCK FUNCTIONALITY IN REGENERATIVE TAPS
    4.
    发明公开
    TRANSPARENT CLOCK FUNCTIONALITY IN REGENERATIVE TAPS 审中-公开

    公开(公告)号：US20230319367A1

    公开(公告)日：2023-10-05

    申请号：US17695780

    申请日：2022-03-15

    Applicant: Charter Communications Operating, LLC

    Inventor： Charles Cook

    IPC: H04L7/00 ,  H04M7/12

    CPC classification number: H04L7/0041 ,  H04M7/1215 ,  H04M7/1235

    Abstract: Within a regeneration device, regenerate a first input signal having a first timestamp and an inadequate signal-to-noise ratio and bypass a second input signal having a second timestamp and having an adequate signal-to-noise ratio. With a central processing server coupled to the device, obtain, from a delay tracking database, a first delay associated with a first signal path for the first input signal and a second delay associated with a second signal path for the second input signal. With the server, cause to be sent downstream the regenerated first input signal together with the first timestamp and the first delay, and the non-regenerated second input signal together with the second timestamp and the second delay.

    TIME-BASED DECISION FEEDBACK EQUALIZATION
    5.
    发明申请
    TIME-BASED DECISION FEEDBACK EQUALIZATION 审中-公开

    公开(公告)号：US20180351770A1

    公开(公告)日：2018-12-06

    申请号：US15806901

    申请日：2017-11-08

    Applicant: Regents of the University of Minnesota

    Inventor： Po-Wei Chiu ,  Somnath Kundu ,  Hyung-il Kim

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03057 ,  H04L7/0041 ,  H04L7/0087 ,  H04L25/03031 ,  H04L2025/03471 ,  H04L2025/03783

    Abstract: A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

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