公开(公告)号：US06784697B2

公开(公告)日：2004-08-31

申请号：US10272102

申请日：2002-10-15

申请人： Swee Yew Choe

发明人： Swee Yew Choe

IPC分类号： H03K1920

CPC分类号： H03K19/1738

摘要： Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

摘要翻译： 具有读出放大器和关断的时钟半轨差分逻辑电路由延迟时钟激活，并且包括由第二延迟时钟和截止装置触发的读出放大器电路。 读出放大器电路的添加和第二延迟时钟信号允许读出放大器电路充当驱动器，因此不需要增加差分逻辑网络的大小以提供驱动器功能。 关闭装置的添加提供了具有切断的半轨差分逻辑电路，其不经历现有技术的半轨差分逻辑电路所经历的大的或“倾斜”，因此功率效率更高。

公开(公告)号：US06750681B2

公开(公告)日：2004-06-15

申请号：US10229660

申请日：2002-08-27

申请人： James Wei

发明人： James Wei

IPC分类号： H03K1920

CPC分类号： H03K19/09432

摘要： An integrated circuit logic topology or architecture suitable for low voltage differential logic operating at radio frequencies is disclosed. The topology, referred to as enhanced pseudo common mode logic, is similar to and compatible with traditional CML, and provides the additional advantage of eliminating the need for level conversion between consecutive logic gates, thereby increasing the potential maximum operating frequency of subsystems implemented using the invention. The invention retains most of the advantages of traditional CML, and in addition permits the independent selection of output logic high level and output logic low level so that they may be matched with the succeeding circuit input levels.

公开(公告)号：US06720797B2

公开(公告)日：2004-04-13

申请号：US09726607

申请日：2000-12-01

申请人： Mitsuru Sasaki

发明人： Mitsuru Sasaki

IPC分类号： H03K1920

CPC分类号： H03K19/1737 ,  G06F17/505 ,  G06F2217/78

摘要： A pass transistor circuit comprises a plurality of pass transistors connected in parallel. The same input signal is inputted into the sources of these pass transistors. Continuities of these pass transistors are controlled by a plurality of control signals having an exclusive relationship therebetween. A plurality of buffers respectively drive the drive segments including at least the pass transistors and wirings. The drive segments being a plurality of divided ranges each having an equal potential.

摘要翻译： 传输晶体管电路包括并联连接的多个传输晶体管。 相同的输入信号被输入到这些通过晶体管的源极中。 这些通过晶体管的连续性由其间具有排他关系的多个控制信号控制。 多个缓冲器分别驱动至少包括传输晶体管和布线的驱动段。 驱动段是各自具有相等电位的多个分割范围。

公开(公告)号：US06700413B1

公开(公告)日：2004-03-02

申请号：US10266671

申请日：2002-10-09

申请人： Ming-Chung Chou

发明人： Ming-Chung Chou

IPC分类号： H03K1920

CPC分类号： H03K19/212 ,  H03K19/086

摘要： A symmetric current mode logic with symmetric input loads as well as identical input logic levels at the input terminals so as to prevent phase error due to level adjustment and to further avoid signal surges due to current steering by parallel switching.

摘要翻译： 具有对称输入负载的对称电流模式逻辑以及输入端子处的相同输入逻辑电平，以防止由于电平调整引起的相位误差，并进一步避免由于并联开关导致的电流转向引起的信号浪涌。

公开(公告)号：US06621294B2

公开(公告)日：2003-09-16

申请号：US10037660

申请日：2002-01-03

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Chorng-Lii Hwang

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Chorng-Lii Hwang

IPC分类号： H03K1920

CPC分类号： H03K19/1737

摘要： The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.

摘要翻译： 本发明提供了一种用于集成电路或装置的焊盘系统。 垫系统包括具有至少一个焊盘输入端子的逻辑电路，用于连接至少一个焊盘和至少两个用于连接到集成电路或设备的至少一个电路系统的输出端子。 逻辑电路可配置为在集成电路或器件的至少一个电路系统的至少两个点之间选择性地连接至少一个焊盘。

公开(公告)号：US06570409B2

公开(公告)日：2003-05-27

申请号：US09827412

申请日：2001-04-06

申请人： Priya Ananthanarayanan ,  Gajendra P. Singh

发明人： Priya Ananthanarayanan ,  Gajendra P. Singh

IPC分类号： H03K1920

CPC分类号： H03K19/09441

摘要： A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.

公开(公告)号：US06456120B1

公开(公告)日：2002-09-24

申请号：US09707796

申请日：2000-11-08

申请人： Hong-Yi Huang

发明人： Hong-Yi Huang

IPC分类号： H03K1920

CPC分类号： H03K3/356139 ,  G11C7/065

摘要： A capacitor-coupling differential logic circuit handling the output of a differential circuit using coupling capacitors and sense amplifier. The coupling capacitors can couple a control signal to the corresponding internal terminal, i.e., the output terminal of the differential circuit. During evaluation, the differential circuit generates a voltage difference on the internal signal of the internal terminal according to the input signal and the predetermined logic operation. The sense amplifier is used to amplify and output the voltage difference on the internal; signal at the internal terminal.

摘要翻译： 电容耦合差分逻辑电路，使用耦合电容和读出放大器处理差分电路的输出。 耦合电容器可以将控制信号耦合到对应的内部端子，即差分电路的输出端子。 在评估期间，差分电路根据输入信号和预定的逻辑运算产生对内部端子的内部信号的电压差。 读出放大器用于放大和输出内部的电压差; 信号在内部终端。

公开(公告)号：US06373292B1

公开(公告)日：2002-04-16

申请号：US09467547

申请日：1999-12-10

申请人： Swee Yew Choe

发明人： Swee Yew Choe

IPC分类号： H03K1920

CPC分类号： H03K19/1738

摘要： A low voltage differential circuit is described herein including a complementary logic tree having first, second and third inputs and two outputs, the logic tree for performing a desired logical function on signals received the the first input, thereby opening a pathway for current flow between at least one of the following: the second input and the first output, the second input and the second output, the third input and the first output, the third input and the second output. The circuit further includes a first transistor having a first gate, a first source, and a first drain, the first drain connected to the first output, the first source being connected to a supply voltage, a second transistor having a second gate, a second source, and a second drain, the second source connected to the first gate, the second drain connected to the first drain; and a third transistor having a third gate, a third source, and a third drain, the third source being connected to a supply voltage, the third gate being connected to the second drain, the third drain connected to the second source and the second output.

摘要翻译： 本文描述了一种低压差分电路，其包括具有第一，第二和第三输入和两个输出的互补逻辑树，用于在接收到第一输入的信号上执行期望的逻辑功能的逻辑树，由此打开用于在 以下中的至少一个：第二输入和第一输出，第二输入和第二输出，第三输入和第一输出，第三输入和第二输出。 电路还包括具有第一栅极，第一源极和第一漏极的第一晶体管，第一漏极连接到第一输出端，​​第一源极连接到电源电压，第二晶体管具有第二栅极，第二晶体管具有第二栅极 源极和第二漏极，第二源极连接到第一栅极，第二漏极连接到第一漏极; 以及具有第三栅极，第三源极和第三漏极的第三晶体管，所述第三源极连接到电源电压，所述第三栅极连接到所述第二漏极，所述第三漏极连接到所述第二源极和所述第二输出端 。

公开(公告)号：US06222391B1

公开(公告)日：2001-04-24

申请号：US08864033

申请日：1997-05-27

申请人： Tetsuya Fujita ,  Tadahiro Kuroda

发明人： Tetsuya Fujita ,  Tadahiro Kuroda

IPC分类号： H03K1920

CPC分类号： H03K19/01812

摘要： A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.

摘要翻译： 为了将形成电流开关的npn双极型晶体管的发射极电位的电平偏移到更高的电位，将用于将输入信号的电位电平向更高电位移动的电路加到传统的差分ECL电路。 因此，ECL电路被改进以确保电流的连续流动并且即使在npn双极晶体管的基极电位被标准ECL电平信号切换的时刻也保持稳定的操作，即使当电源电压在 - 2 V.

公开(公告)号：US06831484B2

公开(公告)日：2004-12-14

申请号：US10648995

申请日：2003-08-27

申请人： Susumu Takano ,  Hiroyuki Takahashi ,  Minoru Nizaka ,  Tomohiro Kitano

发明人： Susumu Takano ,  Hiroyuki Takahashi ,  Minoru Nizaka ,  Tomohiro Kitano

IPC分类号： H03K1920

CPC分类号： H03K19/0948

摘要： A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

摘要翻译： 公开了一种包括逻辑电路的半导体集成电路，其中可以减小解码器面积并且具有减小整个芯片尺寸的效果。 在逻辑电路中包括的MOS FET中，通过输出端子提供电荷的MOS FET以外的阈值电压值低于供给电荷的MOS FET的阈值电压值。 每个MOS FET的栅极宽度的方向垂直于存储单元区域中字线延伸的方向，并且所有MOS FET在与字线延伸的方向垂直的方向上对准。