公开(公告)号：US06836147B2

公开(公告)日：2004-12-28

申请号：US10177180

申请日：2002-06-24

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K1920

CPC分类号： G06F7/501 ,  G06F7/523 ,  H03K19/1736

摘要： A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

摘要翻译： 功能块允许使用少量块实现乘法器和多输入多路复用器。 逻辑功能发生器根据从多个4输入/ 1输出逻辑功能中选择的逻辑功能，根据配置数据，从第一到第四逻辑输入端生成逻辑输出信号。 4-2进位块产生从第二到第四逻辑输入的4-2进位输出。 第一信号至少从逻辑输出产生，来自至少第一逻辑输入的第二信号，来自至少4-2进位输入信号的第三信号和至少4-2进位输入的第四信号 信号。 多路复用器根据第一信号选择第二和第三信号之一以产生进位输出信号。 异或电路产生逻辑输出和第四信号的异或运算结果。

公开(公告)号：US06731138B2

公开(公告)日：2004-05-04

申请号：US10210345

申请日：2002-07-31

申请人： Meiram Heller ,  Eitan Emanuel Rosen

发明人： Meiram Heller ,  Eitan Emanuel Rosen

IPC分类号： H03K1920

CPC分类号： H03K17/005 ,  G06F7/507

摘要： Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.

公开(公告)号：US06690207B1

公开(公告)日：2004-02-10

申请号：US10254251

申请日：2002-09-25

申请人： Kenneth Smetana

发明人： Kenneth Smetana

IPC分类号： H03K1920

CPC分类号： H03K19/086 ,  H03K19/001 ,  H03K19/0866

摘要： A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee2) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee3) that is approximately equal to Vcc−(0.4+(level of series gated logic)(0.9 volts)).

摘要翻译： 提供了高带宽发射极耦合逻辑（ECL）电路。 ECL电路包括具有连接到第一电源（Vcc）的集电极的第一和第二晶体管的射极跟随器电路，以及可操作地连接到比第一电源小约1.5伏的第二电源（Vee2）的发射器。 晶体管接收来自接口CML电路的差分输入信号。 在某些方面，第一电源为3.3伏，第二电源为1.8伏。 CML电路具有接收输入信号的输入端，具有串级门控逻辑电平的逻辑功能，响应输入信号和逻辑功能的第一和第二差分输出信号，并由第一电源和第三电源供电 电源（Vee3）大致等于Vcc-（0.4+（串联门控逻辑电平）（0.9伏特））。

公开(公告)号：US06429691B1

公开(公告)日：2002-08-06

申请号：US09751508

申请日：2000-12-29

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03K1920

CPC分类号： H03K19/017527

摘要： A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

摘要翻译： 电路提供差分逻辑信号，并且包括具有第一差分输入和第二差分输入的差分输入电路。 第一单元接收输入电压信号和用于经由第一节点向第一差分输入提供第一电压的电源电压。 第二单元接收用于经由第二节点向第二差分输入提供第二电压的电源电压。 差分输入电路根据第一和第二电压输出信号。

公开(公告)号：US06414519B1

公开(公告)日：2002-07-02

申请号：US09662443

申请日：2000-09-15

申请人： Brian Lee Abernathy

发明人： Brian Lee Abernathy

IPC分类号： H03K1920

CPC分类号： H03K19/0866 ,  H03K19/00323

摘要： A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.

摘要翻译： 提供差分信号电流模式逻辑（CML）电路，其提供相等的延迟输出。 公约差分逻辑CML电路具有上级和下级晶体管对。 提供给下级的输入信号必须相对于提供给上级的输入而延迟。 本发明提供并行上级部分，使得每个输入信号通过相同数量的晶体管转换成输出。 因此，使与每个输入信号相关联的延迟相等。 提供异或OR，OR和AND电路的具体例子。

公开(公告)号：US06255856B1

公开(公告)日：2001-07-03

申请号：US09382785

申请日：1999-08-25

申请人： Kun-Chang Oh

发明人： Kun-Chang Oh

IPC分类号： H03K1920

CPC分类号： G06F7/026

摘要： A comparator which improves a comparing speed and has a simple logic circuit compared to the conventional adder or subtracter includes: a plurality of pre-comparing units for comparing two inputs A, B by dividing each of the inputs by 4 bits; a selection logic unit for receiving an equality signal among signals from the pre-comparing units and outputting a selection enable signal; a plurality of pass logic units enabled by the selection enable signal of the selection logic unit and outputting outputs of the pre-comparing units and the input A; and a post-comparing unit for receiving and comparing a 4-bit output of the pre-comparing units which is outputted through the enabled pass logic units and the input A.

摘要翻译： 与常规加法器或减法器相比，提高比较速度并具有简单逻辑电路的比较器包括：多个预比较单元，用于通过将每个输入除以4位来比较两个输入A，B; 选择逻辑单元，用于在来自所述预比较单元的信号中接收相等信号，并输出选择使能信号; 由选择逻辑单元的选择使能信号使能的多个通过逻辑单元，并输出预比较单元和输入端A的输出; 以及后置比较单元，用于接收和比较通过启用通过逻辑单元输出的预比较单元的4位输出和输入A.

公开(公告)号：US06252427B1

公开(公告)日：2001-06-26

申请号：US09333048

申请日：1999-06-15

申请人： Shinichi Domae ,  Tetsuya Ueda

发明人： Shinichi Domae ,  Tetsuya Ueda

IPC分类号： H03K1920

CPC分类号： H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： To prevent a void from being formed in a CMOS inverter due to electromigration. A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. one terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21, while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.

摘要翻译： 为了防止由于电迁移而在CMOS反相器中形成空隙。电源线11经由第一触点12连接到p沟道MOS晶体管Tr1的源极。地线13连接到n的源极 通道MOS晶体管Tr2经由第二触点14.第一输出信号线15的一个端子经由第三触点16连接到p沟道MOS晶体管Tr1的漏极，而另一端连接到 n沟道MOS晶体管Tr2经由第四触点17.第二输出信号线18的一个端子连接到第四触点17，而另一端延伸到逆变器的输出端。 输入信号线19的第一路径经由第五接点21连接到p沟道MOS晶体管Tr1的栅电极20，其第二路径连接到n沟道MOS晶体管Tr2的栅电极20 经由第六接触件22。

公开(公告)号：US06218867B1

公开(公告)日：2001-04-17

申请号：US09217809

申请日：1998-12-22

申请人： Shigeki Imai ,  Kazuya Fujimoto

发明人： Shigeki Imai ,  Kazuya Fujimoto

IPC分类号： H03K1920

CPC分类号： H03K19/1737

摘要： A pass transistor circuit of the present invention includes a plurality of pass transistor sections having pass transistor logics and has a logic functionality which is based on a pass transistor logic functionality of a plurality of pass transistor sections. One or more of the pass transistor sections is a CMOSFET formed of a p-type MOSFET and an n-type MOSFET. At least one of the p-type MOSFET and the n-type MOSFET of the CMOSFET is a transistor having a TFT structure.

摘要翻译： 本发明的传输晶体管电路包括具有传输晶体管逻辑的多个传输晶体管部分，并且具有基于多个传输晶体管部分的传输晶体管逻辑功能的逻辑功能。 一个或多个传输晶体管部分是由p型MOSFET和n型MOSFET形成的CMOSFET。 CMOSFET的p型MOSFET和n型MOSFET中的至少一个是具有TFT结构的晶体管。

公开(公告)号：US06188240B1

公开(公告)日：2001-02-13

申请号：US09325339

申请日：1999-06-04

申请人： Shogo Nakaya

发明人： Shogo Nakaya

IPC分类号： H03K1920

CPC分类号： G06F7/503 ,  G06F2207/3876 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal, a core logic carry generation output terminal, a core logic carry propagation output terminal, a ripple-core logic carry input terminal, and a sum output terminal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0”. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit. A carry logic circuit has a ripple carry input terminal, a ripple carry output terminal, a ripple-core logic carry output terminal, a core logic carry generation input terminal, and a core logic carry propagation input terminal.

摘要翻译： 可编程功能块包括具有由第一到第四参数输入端子组成的第一参数输入组的核心逻辑电路，由第一至第四参数输入端子组成的第二参数输入组，第一至第三配置输入端子， 终端，核心逻辑携带产生输出终端，核心逻辑携带传播输出终端，纹波核心逻辑进位输入终端和和输出终端。 连接到互连线和第一和第二自变量输入组，输入块包括第八输入选择单元，用于在互连线上选择八个输入选择的信号中的八个信号，固定逻辑值“1”，以及 固定逻辑值为“0”。 第一至第三存储电路分别连接到第一至第三配置输入端，作为第一至第三存储逻辑值，存储一位的逻辑值。 进位逻辑电路具有纹波输入端子，纹波输入端子，纹波纹逻辑输入端子，核心逻辑进位产生输入端子和核心逻辑进位传播输入端子。

公开(公告)号：US06819142B2

公开(公告)日：2004-11-16

申请号：US10387733

申请日：2003-03-13

申请人： Hans-Heinrich Viehmann ,  Stefan Lammers

发明人： Hans-Heinrich Viehmann ,  Stefan Lammers

IPC分类号： H03K1920

CPC分类号： H03K19/018528 ,  H03K19/0016

摘要： An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.

摘要翻译： 一种用于将差分模式信号转换成具有降低的功耗的单端信号的装置。 优选实施例包括单端转换器（例如，单端转换器505）和输出晶体管（例如，输出晶体管524），当单端转换器505处于待机状态时，可以将单端转换器505的输出 到一个已知的逻辑状态（如高逻辑或低逻辑）。 单端缓冲器（反相或非反相）可用于输出信号兼容性转换。