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公开(公告)号：US07836324B2
公开(公告)日：2010-11-16
申请号：US11740452
申请日：2007-04-26
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译： 在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。 控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。 该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。 数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。 控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。
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公开(公告)号：US08027213B2
公开(公告)日：2011-09-27
申请号：US12488121
申请日：2009-06-19
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C2029/5006
摘要： A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.
摘要翻译： 用于测量集成电路上的SRAM单元的读取电流的可变性的机构包括具有包括多个SRAM单元的SRAM阵列的集成电路。 集成电路还可以包括被配置为响应于选择输入来选择特定SRAM单元的选择电路。 例如集成电路上的诸如环形振荡器的振荡器电路可被配置为以在第一模式下操作期间取决于所选择的SRAM单元的读取电流的频率进行振荡。 耦合到振荡器电路的频率确定电路可以被配置为输出与振荡器电路的振荡频率相对应的值。
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公开(公告)号：US20050030064A1
公开(公告)日：2005-02-10
申请号：US10637285
申请日：2003-08-08
IPC分类号： G11C7/10 , H03K5/135 , H03K19/003 , H03L7/00 , H03L7/081 , H03K19/094
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , H03K5/135 , H03K19/00323 , H03L7/00 , H03L7/0812
摘要： A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.
摘要翻译： 自校正I / O接口驱动器方案使用延迟差检测器来检测I / O数据路径和I / O时钟路径之间的延迟差异。 延迟差检测器输入来自连接到I / O数据通路的数据输出引脚的信号和连接到I / O时钟通路的时钟输出引脚。 在确定来自数据和时钟输出引脚的信号之间的延迟差时，延迟差检测器向I / O数据通路和I / O时钟通路中的一个或多个驱动器产生信号。 来自延迟差检测器的这些信号用于有效地调整一个或多个驱动器的延迟，以便有效地减少I / O数据路径和I / O时钟路径之间的延迟差。
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公开(公告)号：US06829548B2
公开(公告)日：2004-12-07
申请号：US10406541
申请日：2003-04-03
IPC分类号： G06F1100
CPC分类号： H03L7/0812 , G01R25/005
摘要： An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.
摘要翻译： 用于测量延迟锁定环路中的静态相位误差的装置包括第一测试阶段和第二测试阶段。 第一测试阶段接收参考时钟，芯片时钟和控制信号。 与第一测试级并行，第二测试级接收参考时钟，芯片时钟和控制信号的补码。 根据控制信号，第一测试级输出第一测试信号，并且根据控制信号的补码，第二测试级输出第二测试信号。 第一测试信号和第二测试信号用于根据控制信号和控制信号的补码产生一组静态相位误差测量值。 通过对静态相位误差测量值进行平均，对延迟锁定环路测量静态相位误差。
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公开(公告)号：US08307236B2
公开(公告)日：2012-11-06
申请号：US12912521
申请日：2010-10-26
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译： 在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。 控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。 该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。 数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。 控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。
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6.发明授权Apparatus and method for testing level shifter voltage thresholds on an integrated circuit 有权在集成电路上测试电平移位器电压阈值的装置和方法公开(公告)号：US07977998B2
公开(公告)日：2011-07-12
申请号：US12481253
申请日：2009-06-09
IPC分类号： H03L5/00
CPC分类号： H03K19/018507 , G01R31/318555 , G01R31/318572
摘要： An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.
摘要翻译： 用于在集成电路上测试电平移位器阈值电压的装置和方法包括一个或多个电平移位器模块，每个电平移位器模块包括多个电平移位器电路。 每个电平移位器电路可以耦合到第一和第二电压源。 每个电平移位器电路还可以接收参考第一电压源的输入信号，并产生参考第二电压源的输出信号。 此外，每个电平移位器模块可以包括可以检测每个电平移位器电路的输出值的检测逻辑。 控制电路可以被配置为迭代地改变来自一个电压源的电压输出，并且在输入信号被提供给电平移位器电路的同时保持另一个电压源上的电压。 检测逻辑可以在每次电压变化时捕获输出值。
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7.发明申请APPARATUS AND METHOD FOR TESTING LEVEL SHIFTER VOLTAGE THRESHOLDS ON AN INTEGRATED CIRCUIT 有权在集成电路上测试水平变压器电压的装置和方法公开(公告)号：US20100308887A1
公开(公告)日：2010-12-09
申请号：US12481253
申请日：2009-06-09
IPC分类号： H03L5/00
CPC分类号： H03K19/018507 , G01R31/318555 , G01R31/318572
摘要： An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.
摘要翻译： 用于在集成电路上测试电平移位器阈值电压的装置和方法包括一个或多个电平移位器模块，每个电平移位器模块包括多个电平移位器电路。 每个电平移位器电路可以耦合到第一和第二电压源。 每个电平移位器电路还可以接收参考第一电压源的输入信号，并产生参考第二电压源的输出信号。 此外，每个电平移位器模块可以包括可以检测每个电平移位器电路的输出值的检测逻辑。 控制电路可以被配置为迭代地改变来自一个电压源的电压输出，并且在输入信号被提供给电平移位器电路的同时保持另一个电压源上的电压。 检测逻辑可以在每次电压变化时捕获输出值。
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公开(公告)号：US06859068B1
公开(公告)日：2005-02-22
申请号：US10637285
申请日：2003-08-08
IPC分类号： G11C7/10 , H03K5/135 , H03K19/003 , H03L7/00 , H03L7/081 , H03K19/094
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , H03K5/135 , H03K19/00323 , H03L7/00 , H03L7/0812
摘要： A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.
摘要翻译： 自校正I / O接口驱动器方案使用延迟差检测器来检测I / O数据路径和I / O时钟路径之间的延迟差异。 延迟差检测器输入来自连接到I / O数据通路的数据输出引脚的信号和连接到I / O时钟通路的时钟输出引脚。 在确定来自数据和时钟输出引脚的信号之间的延迟差时，延迟差检测器向I / O数据通路和I / O时钟通路中的一个或多个驱动器产生信号。 来自延迟差检测器的这些信号用于有效地调整一个或多个驱动器的延迟，以便有效地减少I / O数据路径和I / O时钟路径之间的延迟差。
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公开(公告)号：US06831487B2
公开(公告)日：2004-12-14
申请号：US10393303
申请日：2003-03-20
IPC分类号： H03B2100
CPC分类号： H03K17/164
摘要： A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.
摘要翻译： 驱动器级使用主驱动器和次驱动器来平衡驱动电流，以便在发送与紧随新数据位之前连续发送的位不同的新数据位时。 每当发送数据位时，主驱动器激活下拉器件和上拉器件中的一个。 当检测到两个或多个连续的传输时，辅助驱动器激活其下拉装置中的一个和上拉装置。 在这种情况下，由第二驱动器减少由第一连续位引起的驱动级的电流。
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公开(公告)号：US06570409B2
公开(公告)日：2003-05-27
申请号：US09827412
申请日：2001-04-06
IPC分类号： H03K1920
CPC分类号： H03K19/09441
摘要： A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.
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