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公开(公告)号：US20230215331A1
公开(公告)日：2023-07-06
申请号：US18119787
申请日：2023-03-09
Inventor： Xuehuan FENG , Yongqian LI
CPC classification number: G11C19/28 , G09G3/20 , G09G2310/0286
Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, and a first pull-down circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal.
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公开(公告)号：US11688318B2
公开(公告)日：2023-06-27
申请号：US17555695
申请日：2021-12-20
Inventor： Xuehuan Feng , Yongqian Li
CPC classification number: G09G3/20 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.
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353.发明公开公开(公告)号：US20230162642A1
公开(公告)日：2023-05-25
申请号：US17628876
申请日：2021-01-22
Inventor： Song MENG
IPC: G09G3/20 , G09G3/3275
CPC classification number: G09G3/2007 , G09G3/3275 , G09G2300/0819 , G09G2340/02 , G09G2360/145 , G09G2360/128
Abstract: The present disclosure relates to the field of display technology, and provides a display panel and a driving method thereof, a compensation data compression method and a compensation data decompression method. The display panel includes a data compression unit and a data decompression unit. The data compression unit is used to acquire a plurality of first compensation data and a common parameter, and compress each of the first compensation data into second compensation data according to a preset compression rule based on the first compensation data and the common parameter. The data decompression unit is used to acquire a plurality of second compensation data and the common parameter, and decompress each of the second compensation data into the first compensation data according to a preset decompression rule based on the second compensation data and the common parameter.
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公开(公告)号：US11645968B2
公开(公告)日：2023-05-09
申请号：US17424483
申请日：2020-08-24
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/20 , G11C19/28
CPC classification number: G09G3/2092 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G11C19/28
Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, a first pull-down circuit and a unidirectional isolation circuit, and the first output terminal is connected to the first pull-down circuit by the unidirectional isolation circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.
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公开(公告)号：US11620934B2
公开(公告)日：2023-04-04
申请号：US17424486
申请日：2020-08-25
Inventor： Xuehuan Feng , Yongqian Li
Abstract: The invention provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. Wherein, the shift register comprises: a display control circuit connected to a pull-up node, a first power terminal and a first control terminal; a sensing control circuit connected to the pull-up node, a second control terminal and a third control terminal and configured to store a potential of the pull-up node in a display mode under the control of the second control terminal and write the stored potential into the pull-up node in a sensing mode under the control of the third control terminal; and a first output circuit connected to the pull-up node, a first clock terminal and a first output terminal.
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Patent Agency Ranking
公开(公告)号：US20230091012A1
公开(公告)日：2023-03-23
申请号：US17439522
申请日：2021-02-09
Inventor： Zhidong YUAN , Yongqian LI , Meng LI , Can YUAN , Min HE , Chao JIAO
IPC: G09G3/3233
Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal. A first terminal of the second control circuit is connected to the first multiplexing signal line. A second terminal of the second control circuit is used for receiving a first data signal.
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357.发明申请公开(公告)号：US20230084572A1
公开(公告)日：2023-03-16
申请号：US17798673
申请日：2021-11-10
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3208
Abstract: A method for compensating display brightness, a circuit for compensating display brightness, and a display device are provided. The method for compensating display brightness is applicable to a display device. A first group of sub-pixel rows in the display device perform normal display and black frame insertion display in a same frame display period. A second group of sub-pixel rows in the display device perform normal display in a current frame display period and an adjacent next frame display period, and perform black insertion display in the adjacent next frame display period. A first interval period is provided between the current frame display period and the adjacent next frame display period. The method for compensating includes: compensating luminous brightness of the first group of sub-pixel rows and/or compensating luminous brightness of the second group of sub-pixel rows.
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公开(公告)号：US20230025310A1
公开(公告)日：2023-01-26
申请号：US17780626
申请日：2021-07-21
Inventor： Xuehuan FENG , Xing YAO , Jingbo XU , Xuelian CHENG
IPC: G09G3/20 , G09G3/3266
Abstract: Provided is a method for driving a display device, including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1st to ath rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1st to bth rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period.
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359.发明授权公开(公告)号：US11562673B2
公开(公告)日：2023-01-24
申请号：US17015475
申请日：2020-09-09
Inventor： Xuehuan Feng , Pan Xu
Abstract: The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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公开(公告)号：US11545093B2
公开(公告)日：2023-01-03
申请号：US17427607
申请日：2021-01-22
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G5/00 , G09G3/3266 , G11C19/28 , G09G3/20
Abstract: A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.
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