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公开(公告)号：US20220284853A1
公开(公告)日：2022-09-08
申请号：US17701615
申请日：2022-03-22
Inventor： Wenchao BAO , Song MENG , Min HE , Huihui LI
IPC: G09G3/3225 , H05K1/18 , H01L51/52 , G09G3/00
Abstract: A display module includes a display panel, a power supply driver, a voltage signal line, a sampling resistor and a detection and control circuit. The voltage signal line is connected between the display panel and the power supply driver. The sampling resistor is connected in series with the voltage signal line. The detection and control circuit is connected to two ends of the sampling resistor and the power supply driver. The detection and control circuit is configured to: detect a voltage across the sampling resistor or a current flowing through the sampling resistor; and control the power supply driver to generate a driving voltage equal to a preset value lower than a voltage threshold, if determining that the voltage across the sampling resistor is greater than or equal to the voltage threshold, or if determining that the current is greater than or equal to a current threshold.
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公开(公告)号：US11437440B2
公开(公告)日：2022-09-06
申请号：US16963346
申请日：2019-09-27
Inventor： Can Yuan , Yongqian Li , Pan Xu , Zhidong Yuan , Meng Li , Xuehuan Feng , Zehua Ding
IPC: H01L29/08 , H01L27/32 , G09G3/3225
Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.
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公开(公告)号：US20220269123A1
公开(公告)日：2022-08-25
申请号：US17478267
申请日：2021-09-17
Inventor： Huihui LI , Wenchao BAO , Song MENG
IPC: G02F1/1345
Abstract: The present disclosure provides a chip on film and a display device. The chip on film includes: a first end, wherein a first row of bonding terminals and a second row of bonding terminals are arranged on a first surface of the first end, the first row of bonding terminals and the second row of bonding terminals are spaced apart and insulated from each other, and the first row of bonding terminals is closer to a center of the chip on film than the second row of bonding terminals; and a plurality of leads, extending in a second direction and including a first part and a second part. A first end section of each lead of the first part serves as one of the first row of bonding terminals, a first end section of each lead of the second part serves as one of the second row of bonding terminals.
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公开(公告)号：US20220189406A1
公开(公告)日：2022-06-16
申请号：US17352319
申请日：2021-06-20
Inventor： Xuehuan FENG , Yongqian LI , Pan XU
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.
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公开(公告)号：US11361715B1
公开(公告)日：2022-06-14
申请号：US17352319
申请日：2021-06-20
Inventor： Xuehuan Feng , Yongqian Li , Pan Xu
IPC: G09G3/36 , G09G3/3266 , G09G3/3225 , G11C19/28 , H03K19/20
Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.
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Patent Agency Ranking
公开(公告)号：US11361696B2
公开(公告)日：2022-06-14
申请号：US17052135
申请日：2019-08-08
Inventor： Xuehuan Feng , Yongqian Li
Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.
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公开(公告)号：US20220165977A1
公开(公告)日：2022-05-26
申请号：US17489641
申请日：2021-09-29
Inventor： Wentong HUANG , Rui PENG , Xiaoning LIU
Abstract: Provided is a display panel. The display panel includes a substrate, an anode layer, a planarization layer and an organic functional layer. The anode layer is disposed on a side of the substrate, the planarization layer is disposed on a side of the anode layer away from the substrate and configured to cover the anode layer, and the organic functional layer is disposed on a side of the planarization layer away from the anode layer.
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公开(公告)号：US11341923B2
公开(公告)日：2022-05-24
申请号：US17206121
申请日：2021-03-19
Inventor： Zhidong Yuan , Pan Xu , Yongqian Li , Can Yuan
IPC: G09G3/3266 , G11C19/28 , G09G3/3233
Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.
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公开(公告)号：US11328785B2
公开(公告)日：2022-05-10
申请号：US17104809
申请日：2020-11-25
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.
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公开(公告)号：US20220130926A1
公开(公告)日：2022-04-28
申请号：US17506532
申请日：2021-10-20
Inventor： Xinxin WANG , Minghung HSU
Abstract: Provided is a display panel, including: a backplane; a first electrode and an auxiliary layer, disposed on a same side of the backplane, wherein a distance between a surface of the first electrode distal from the backplane and the backplane is shorter than or equal to a distance between a surface of the auxiliary layer distal from the backplane and the backplane; a pixel defining layer, at least partially disposed on a side of the auxiliary layer distal from the backplane; a second electrode, disposed on a side of the pixel defining layer distal from the backplane; and an auxiliary electrode, disposed on a side of the second electrode distal from the backplane, wherein an orthographic projection of the auxiliary electrode onto the backplane is located within an orthographic projection of the pixel defining layer onto the backplane.
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