Regulating device
    371.
    发明申请
    Regulating device 有权
    调节装置

    公开(公告)号:US20010030531A1

    公开(公告)日:2001-10-18

    申请号:US09750612

    申请日:2000-12-28

    Inventor: Laurent Micheli

    CPC classification number: G05F1/569 G05F1/571

    Abstract: A regulating device for receiving a variable voltage and delivering a constant voltage includes a regulating element that includes a circuit for comparing the variable voltage with a reference voltage, a circuit for dividing the variable voltage by a factor, and a switching circuit for supplying the regulating element with a voltage equal either to the variable voltage or to the divided variable voltage. The switching circuit may be controlled by the comparison circuit in such a way that the regulating element is supplied with the variable voltage if a voltage condition is not satisfied and with the divided variable voltage if the voltage condition is satisfied.

    Abstract translation: 用于接收可变电压并传送恒定电压的调节装置包括调节元件,该调节元件包括用于将可变电压与参考电压进行比较的电路,用于将可变电压除以因数的电路和用于提供调节 元件的电压等于可变电压或分压可变电压。 切换电路可以由比较电路控制,使得如果不满足电压条件,则调节元件被提供可变电压,并且如果满足电压条件,则具有分压的可变电压。

    Integrated circuit comprising an output transistor with a controlled fall time
    372.
    发明申请
    Integrated circuit comprising an output transistor with a controlled fall time 失效
    集成电路包括具有受控下降时间的输出晶体管

    公开(公告)号:US20010017559A1

    公开(公告)日:2001-08-30

    申请号:US09742890

    申请日:2000-12-21

    CPC classification number: H03K17/163

    Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

    Abstract translation: 集成电路被电压提供电压,并且包括具有由逻辑电路的输出驱动的栅极的输出MOS晶体管和用于偏置输出MOS晶体管的栅极的电路。 用于偏置栅极的电路被提供用于相对于否则将由逻辑电路的输出提供的栅极 - 源偏置电压降低导通状态下的输出MOS晶体管的栅极 - 源极偏置电压。 本发明特别适用于I2C总线的输出级。

    Voltage regulator with a ballast transistor and current limiter
    373.
    发明申请
    Voltage regulator with a ballast transistor and current limiter 有权
    具有镇流器和限流器的稳压器

    公开(公告)号:US20010005129A1

    公开(公告)日:2001-06-28

    申请号:US09735392

    申请日:2000-12-11

    Inventor: Claude Renous

    CPC classification number: G05F1/565 G05F1/5735 Y10S323/908

    Abstract: A voltage regulator with a current limiter includes a voltage regulating circuit including an amplifier circuit and a feedback circuit. The amplifier circuit includes a ballast or pass resistor and the feedback circuit supplies a first feedback voltage to the amplifier circuit, which is compared to a reference voltage. The voltage regulator further includes a current limiter circuit including a current limiter transistor in series with the ballast transistor and an output of the voltage regulator and a feedback circuit supplying a second feedback voltage to a controller for controlling the current limiter transistor. The controller causes the current limiter transistor to operate between saturation and blocking conditions depending on whether the second feedback voltage, which is representative of the output of the voltage regulator, is above or below a predetermined threshold voltage.

    Abstract translation: 具有限流器的电压调节器包括具有放大器电路和反馈电路的电压调节电路。 放大器电路包括镇流器或通过电阻器,并且反馈电路向放大器电路提供第一反馈电压,其与参考电压进行比较。 电压调节器还包括电流限制器电路,该限流器电路包括与镇流器晶体管串联的限流晶体管和电压调节器的输出端以及向控制器提供第二反馈电压的反馈电路,用于控制限流晶体管。 控制器根据表示电压调节器的输出的第二反馈电压是否高于或低于预定阈值电压,使得限流晶体管在饱和和阻塞条件之间工作。

    Secured master-slave D type flip-flop circuit
    374.
    发明申请
    Secured master-slave D type flip-flop circuit 有权
    安全主从D型触发器电路

    公开(公告)号:US20010004220A1

    公开(公告)日:2001-06-21

    申请号:US09740269

    申请日:2000-12-19

    Inventor: Alain Pomet

    CPC classification number: G06K19/073 H03K3/0372 H03K3/35625

    Abstract: A master-slave D type flip-flop circuit includes a power consumption circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

    Abstract translation: 主从D型触发器电路包括功率消耗电路,其包括与主触发器电路并联的参考级和触发器电路的从动级。 该结构有利地提供触发器电路在时钟信号的前沿和后沿的每一个上的切换,用于触发器电路的排序。

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