公开(公告)号：US20030133344A1

公开(公告)日：2003-07-17

申请号：US10352581

申请日：2003-01-28

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

公开(公告)号：US20040164788A1

公开(公告)日：2004-08-26

申请号：US10721058

申请日：2003-11-24

Applicant: STMicroelectronics S.A.

Inventor： Jean Devin

IPC: G05F001/10

CPC classification number: H02H9/046

Abstract: An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

Abstract translation: 一种具有提供确定电压的电压发生器的集成电路，布置在电压发生器的输出端的限压电路，该限压电路具有由二极管配置的MOS晶体管形成的至少一个PN结，该PN结具有 限定阈值的击穿电压，用于触发由PN结接通的雪崩效应的电压限制电路，与PN结串联的至少一个负载，用于限制当PN结处于PN结处时通过PN结的雪崩电流 以及与PN结和负载并联的至少一个开关，当PN结关闭时，开关布置成处于断开状态，并且当PN结接通时处于闭合状态。

公开(公告)号：US20020119625A1

公开(公告)日：2002-08-29

申请号：US09997214

申请日：2001-11-15

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: H01L021/336

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract translation: 可由页面擦除的闪速存储器包括包含以页面排列的多个浮置栅极晶体管的闪存阵列，以及用于检查浮置栅极晶体管的阈值电压的检查电路。 具有小于给定阈值的阈值电压的编程晶体管被重新编程。 检查电路包括由至少一行浮动栅极晶体管形成的非易失性计数器，用于读取计数器中要检查的页面的地址的读取电路和用于在页面已经被加载之后递增计数器的递增电路 检查。

公开(公告)号：US20010017559A1

公开(公告)日：2001-08-30

申请号：US09742890

申请日：2000-12-21

Applicant: STMicroelectronics S.A.

Inventor： Bertrand Bertrand ,  Jean Devin

IPC: H03K005/12

CPC classification number: H03K17/163

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract translation: 集成电路被电压提供电压，并且包括具有由逻辑电路的输出驱动的栅极的输出MOS晶体管和用于偏置输出MOS晶体管的栅极的电路。 用于偏置栅极的电路被提供用于相对于否则将由逻辑电路的输出提供的栅极 - 源偏置电压降低导通状态下的输出MOS晶体管的栅极 - 源极偏置电压。 本发明特别适用于I2C总线的输出级。