公开(公告)号：US20250107230A1

公开(公告)日：2025-03-27

申请号：US18473861

申请日：2023-09-25

Applicant: STMicroelectronics International N.V.

Inventor： Franck JULIEN

IPC: H01L27/12 ,  H01L21/84

Abstract: A transistor device comprising a silicon-on-insulator (SOI) substrate having a plurality of polysilicon gates including a plurality of recessed gates and a plurality of non-recessed gates. The plurality of recessed gates being recessed in a top silicon layer of the SOI substrate and the plurality of non-recessed gates being on the top silicon layer. The plurality of recessed gates comprising an upper cap portion on a bottom buried portion that is in a recess of the SOI substrate. Methods of manufacturing the device are provided.

公开(公告)号：US20250105875A1

公开(公告)日：2025-03-27

申请号：US18886196

申请日：2024-09-16

Applicant: STMicroelectronics International N.V.

Inventor： Marc HOUDEBINE ,  Sylvain MAJCHERCZAK ,  Florent SIBILLE

IPC: H04B5/20 ,  H04B5/48

Abstract: A device of contactless communication by active load modulation includes a receive circuit configured to receive as an input a reception signal originating from an electromagnetic field intended to be received by an antenna and to deliver as an output a first clock signal. A transmit circuit includes an output coupled to the antenna and operates to deliver on its output a modulation signal in phase with the reception signal. A compensation circuit is configured to compensate for a first delay of the first clock signal due to the receive circuit and to the amplitude of the reception signal. The compensation circuit operates to determine a phase-shift value to be applied to an input signal of the transmit circuit to compensate for the first delay.

公开(公告)号：US20250105227A1

公开(公告)日：2025-03-27

申请号：US18890617

申请日：2024-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Jonathan GODILLON

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/64

Abstract: An electronic circuit includes a first die, having a GaN transistor, and a second die, stacked so that an element of the second die electrically connects a first node and a second nodes of the first die respectively coupled to a conduction node and to a control node of the GaN transistor.

公开(公告)号：US20250103864A1

公开(公告)日：2025-03-27

申请号：US18472063

申请日：2023-09-21

Applicant: STMicroelectronics International N.V.

Inventor： Federico RIZZARDINI ,  Giacomo TURATI

IPC: G06N3/0464

Abstract: A device includes a sensor and processing circuitry. The sensor, in operation, generates a sequence of data samples. The processing circuitry, in operation, implements a sliding convolutional neural network (SCNN) having a plurality of layers to generate classification results based on the sequence of data samples. The SCNN sequentially processes the sequence of data samples, the sequentially processing the sequence of data samples including, for each received sample of a set of received data samples of the sequence of data samples, iteratively updating partial results of an inference of a first layer of the plurality of layers based on a respective patch of data samples of the sequence of data samples. The respective patch of data samples includes the received data sample. The classification results may be used to generate control signals, such as by the sensing device or a host processor coupled to the sensing device.

公开(公告)号：US20250103552A1

公开(公告)日：2025-03-27

申请号：US18371173

申请日：2023-09-21

Applicant: STMicroelectronics International N.V.

Inventor： Antonio ANASTASIO

IPC: G06F15/82 ,  G06F1/10 ,  G06F13/40

Abstract: Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

公开(公告)号：US20250103082A1

公开(公告)日：2025-03-27

申请号：US18897333

申请日：2024-09-26

Applicant: STMicroelectronics International N.V.

Inventor： Marc SABUT ,  Emmanuel ALLIER ,  Matthieu DESVERGNE

IPC: G05F3/26 ,  H03F3/45

Abstract: A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes output nodes generating first and second bandgap reference currents. A transconductance amplifier circuit in a current control feedback loop of the bandgap voltage generator circuit has differential inputs which receive base currents. A differential amplifier circuit has inputs configured to receive the first and second bandgap reference currents and includes a compensation current sink circuit configured to sink compensation currents from the first and second bandgap reference currents which correspond to the base current received at the differential inputs of the transconductance amplifier circuit.

公开(公告)号：US20250102391A1

公开(公告)日：2025-03-27

申请号：US18476114

申请日：2023-09-27

Applicant: STMicroelectronics International N.V.

Inventor： Luca MAGGI ,  Marco DEL SARTO ,  Alex GRITTI

IPC: G01L19/14 ,  G01L19/00 ,  G01L19/06

Abstract: A sensor module includes an organic substrate, a MEMS pressure sensor mounted to the organic substrate, and a unitary lid mounted on the substrate. The unitary lid includes a central elevated portion housing the MEMS pressure sensor, an aperture in the central elevated portion, and a flat flange extending from the central elevated portion to an edge of the organic substrate.

公开(公告)号：US12261578B2

公开(公告)日：2025-03-25

申请号：US17891860

申请日：2022-08-19

Applicant: STMicroelectronics International N.V.

Inventor： Riju Biswas

IPC: H03F3/45 ,  H03M1/06

Abstract: An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

公开(公告)号：US20250089396A1

公开(公告)日：2025-03-13

申请号：US18825429

申请日：2024-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Arthur ARNAUD

IPC: H01L31/0352 ,  H01L31/028 ,  H01L31/109 ,  H04N25/77

Abstract: A pixel includes a first doped region of a first conductivity type and a second doped region of a second conductivity type. The first doped region includes first and second layers forming a heterojunction. A dopant concentration of the first layer is greater than a dopant concentration of the second layer. The first layer is made of a semiconductor material and the second layer includes quantum dots. The second doped region is in contact with the second layer, with the first layer being laterally surrounded by an insulated conductive wall that is biased to a negative voltage.

公开(公告)号：US20250085881A1

公开(公告)日：2025-03-13

申请号：US18463041

申请日：2023-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Jean-Louis MODAVE ,  Guillaume DOCQUIER

IPC: G06F3/06 ,  G06F7/58

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that shred data stored in a memory unit.