公开(公告)号：US20060109270A1

公开(公告)日：2006-05-25

申请号：US10533458

申请日：2002-11-01

Applicant: Philippe Perey ,  Andrew Gruber

Inventor： Philippe Perey ,  Andrew Gruber

IPC: G06T15/10 ,  G06T15/20

CPC classification number: G09G1/07 ,  G06T15/005 ,  G09B9/003 ,  G09B9/302 ,  G09B9/32 ,  G09B9/36

Abstract: A visual display system uses commercial graphics processing units (GPUs) to determine an occlusion of calligraphic light points (CLPs) in a visual display. A color buffer pointer address of the GPUs is changed to point to a CLP subpixel counter and color datum associated with each CLP is changed to an identifier of the respective CLPs so that an occlusion count of GPU indications can be accumulated.

Abstract translation: 视觉显示系统使用商业图形处理单元（GPU）来确定视觉显示中书法光点（CLPs）的遮挡。 改变GPU的颜色缓冲器指针地址以指向CLP子像素计数器，并且将与每个CLP相关联的颜色基准改变为各个CLP的标识符，使得可以累积GPU指示的遮挡计数。

公开(公告)号：US20050024385A1

公开(公告)日：2005-02-03

申请号：US10633214

申请日：2003-08-01

Applicant: Andrew Gruber

Inventor： Andrew Gruber

IPC: G06T3/40 ,  G06T11/40 ,  G09G5/00

CPC classification number: G06T3/4007 ,  G06T11/40

Abstract: A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geometric values based on the plurality of vertex values, wherein the differential geometric values are independent of a parameter slope between the plurality of vertex values. While in a calculation mode, a first geometric value and second geometric value are determined based on a pixel value, a plurality of vertex values and the differential geometric values. A pixel value is determined for each of the plurality of pixels based on the vertex parameter value, the first geometric value and the second geometric value. Thereupon, pixel parameters may be interpolated on a per-pixel basis reusing the differential geometric values.

Abstract translation: 基于多个顶点值来内插像素参数的方法和装置包括第一操作和设置模式和计算模式。 该方法和装置包括在设置模式下，基于多个顶点值生成多个差分几何值，其中微分几何值与多个顶点值之间的参数斜率无关。 在计算模式中，基于像素值，多个顶点值和微分几何值来确定第一几何值和第二几何值。 基于顶点参数值，第一几何值和第二几何值，为多个像素中的每一个确定像素值。 因此，像素参数可以在每个像素的基础上进行内插，重用差分几何值。

公开(公告)号：US09256429B2

公开(公告)日：2016-02-09

申请号：US13624657

申请日：2012-09-21

Applicant: Lin Chen ,  Yun Du ,  Andrew Gruber

Inventor： Lin Chen ,  Yun Du ,  Andrew Gruber

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887

Abstract: This disclosure describes techniques for selectively activating a resume check operation in a single instruction, multiple data (SIMD) processing system. A processor is described that is configured to selectively enable or disable a resume check operation for a particular instruction based on information included in the instruction that indicates whether a resume check operation is to be performed for the instruction. A compiler is also described that is configured to generate compiled code which, when executed, causes a resume check operation to be selectively enabled or disabled for particular instructions. The compiled code may include one or more instructions that each specify whether a resume check operation is to be performed for the respective instruction. The techniques of this disclosure may be used to reduce the power consumption of and/or improve the performance of a SIMD system that utilizes a resume check operation to manage the reactivation of deactivated threads.

Abstract translation: 本公开描述了用于在单个指令，多数据（SIMD）处理系统中选择性地激活恢复检查操作的技术。 描述了一种处理器，其被配置为基于指示是否对该指令执行恢复检查操作的指令中的信息选择性地启用或禁用特定指令的恢复检查操作。 还描述了一种编译器，其被配置为生成编译代码，其在被执行时导致对特定指令选择性地启用或禁用恢复检查操作。 编译代码可以包括一个或多个指令，每个指令指定是否对相应的指令执行恢复检查操作。 本公开的技术可以用于减少利用恢复检查操作来管理停用线程的重新激活的SIMD系统的功耗和/或提高性能。

公开(公告)号：US08305382B2

公开(公告)日：2012-11-06

申请号：US13253473

申请日：2011-10-05

Applicant: Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06F13/18 ,  G06F15/18

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20070236495A1

公开(公告)日：2007-10-11

申请号：US11277641

申请日：2006-03-28

Applicant: Andrew Gruber ,  Christopher Brennan

Inventor： Andrew Gruber ,  Christopher Brennan

IPC: G06T15/40

CPC classification number: G06T15/405

Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.

Abstract translation: 用于处理像素深度信息的装置和方法通过对当前在像素流水线中的一个或多个像素执行后期Z处理以及进入像素流水线的一个或多个像素的早期Z处理来消除像素流水线中的数据的停止。 该装置和方法还包括确定当前在像素管线中的一个或多个像素的延迟Z处理是否已经完成。 该装置和方法还包括单独执行对进入像素流水线的后续像素的早期Z处理，以响应于确定当前在像素管线中的一个或多个像素的后期Z处理已经完成。 该方法和装置有助于早期和晚期Z数据的并发处理，以避免冲洗像素管道的部分。

公开(公告)号：US20050154864A1

公开(公告)日：2005-07-14

申请号：US10756853

申请日：2004-01-14

Applicant: Norman Rubin ,  Andrew Gruber

Inventor： Norman Rubin ,  Andrew Gruber

IPC: G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/325 ,  G06F9/30072 ,  G06F9/3885

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract translation: 用于嵌套控制流的方法和装置包括具有至少一个上下文比特的处理器。 处理器包括用于执行单指令多数据（SIMD）操作的多个算术逻辑单元。 该方法和装置还包括存储多个指令的第一存储器件，其中多个指令中的每一个指令包括多个额外的位。 处理器可操作以基于额外的比特并结合上下文比特来执行指令。 所述方法和装置还包括第二存储器装置，诸如可操作地耦合到处理器的通用寄存器，第二存储器装置在执行多个指令之一时接收递增计数器指令。 因此，该方法和装置允许通过单个上下文比特结合具有多个额外比特的指令来嵌套控制流。