公开(公告)号：US20130057818A1

公开(公告)日：2013-03-07

申请号：US13414125

申请日：2012-03-07

Applicant: Se Hyoung CHO ,  Hong-Jo PARK ,  Sung Hoon KIM ,  Dong Gyu KIM ,  Dong-Hyeon KI

Inventor： Se Hyoung CHO ,  Hong-Jo PARK ,  Sung Hoon KIM ,  Dong Gyu KIM ,  Dong-Hyeon KI

IPC: G02F1/1343

CPC classification number: G02F1/134363 ,  G02F2001/134345

Abstract: A liquid crystal display includes: two opposing substrates; a liquid crystal layer interposed between the two substrates and including liquid crystal molecules; a gate line which transfers a gate signal; a data line which transfers a data voltage; a voltage transfer line which transfers a voltage having a predetermined magnitude; and pixels, each including first and second pixel electrodes separated from each other, where the first pixel electrode includes first and second subpixel electrode, the second pixel electrode includes third and fourth subpixel electrodes, each of the first to fourth subpixel electrodes includes a stem and branch electrodes, the branch electrodes of the first and third subpixel electrodes are alternately disposed, the branch electrodes of the second and fourth subpixel electrodes are alternately disposed, and a voltage difference between the first and second pixel electrodes is greater than a voltage difference between the second and fourth subpixel electrodes.

Abstract translation: 液晶显示器包括：两个相对的基板; 插入在两个基板之间并包括液晶分子的液晶层; 传输门信号的栅极线; 传送数据电压的数据线; 传送具有预定大小的电压的电压传输线; 以及每个包括彼此分离的第一和第二像素电极的像素，其中所述第一像素电极包括第一和第二子像素电极，所述第二像素电极包括第三和第四子像素电极，所述第一至第四子像素电极中的每一个包括茎和 分支电极，第一和第三子像素电极的分支电极交替设置，第二和第四子像素电极的分支电极交替地布置，并且第一和第二像素电极之间的电压差大于 第二和第四子像素电极。

公开(公告)号：US20130050157A1

公开(公告)日：2013-02-28

申请号：US13410766

申请日：2012-03-02

Applicant: Seung-Soo BAEK ,  Se Hyoung CHO ,  Dong-Gyu KIM ,  Dong-Hyeon KI

Inventor： Seung-Soo BAEK ,  Se Hyoung CHO ,  Dong-Gyu KIM ,  Dong-Hyeon KI

IPC: G09G5/00

CPC classification number: G09G3/2092 ,  G09G3/2022 ,  G09G3/3266 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0281 ,  G09G2310/0286

Abstract: A display device includes: a display panel including a display area, and a peripheral area disposed in the vicinity of the display area; a scan driver including a plurality of stages integrated on the peripheral area; a plurality of gate lines connected to the plurality of stages, respectively; and a plurality of pixel rows in the display area and connected with the plurality of gate lines, respectively. The plurality of stages and the plurality of pixel rows are each arranged in a first direction in a line, the peripheral area includes a fan-out region between the plurality of stages and the plurality of pixel rows, and at least one of the plurality of gate lines in the fan-out region is inclined with respect to the first direction, and a second direction perpendicular to the first direction.

Abstract translation: 显示装置包括：显示面板，包括显示区域和设置在显示区域附近的周边区域; 扫描驱动器，其包括集成在所述外围区域上的多个级; 分别连接到所述多个级的多个栅极线; 以及显示区域中的多个像素行并分别与多个栅极线连接。 所述多个级和所述多个像素行分别沿着第一方向排列，所述周边区域包括所述多个级与所述多个像素行之间的扇出区域，并且所述多个级和所述多个像素行中的至少一个 扇出区域中的栅极线相对于第一方向倾斜，并且垂直于第一方向的第二方向倾斜。

公开(公告)号：US08228282B2

公开(公告)日：2012-07-24

申请号：US11928466

申请日：2007-10-30

Applicant: Byoung-Sun Na ,  Dong-Hyeon Ki ,  Min-Cheol Lee ,  Soon-Il Ahn

Inventor： Byoung-Sun Na ,  Dong-Hyeon Ki ,  Min-Cheol Lee ,  Soon-Il Ahn

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/041

Abstract: In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.

Abstract translation: 在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号 通过输出端子输出到栅极导通电压。 缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。 缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。 因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。

公开(公告)号：US20120013817A1

公开(公告)日：2012-01-19

申请号：US13155868

申请日：2011-06-08

Applicant: Dong-Gyu KIM ,  Hye-Seok NA ,  Mee-Hye JUNG ,  Dong-Hyeon KI ,  Se-Hyoung CHO

Inventor： Dong-Gyu KIM ,  Hye-Seok NA ,  Mee-Hye JUNG ,  Dong-Hyeon KI ,  Se-Hyoung CHO

IPC: G02F1/136

CPC classification number: G02F1/1393 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0452

Abstract: A liquid crystal display device includes a substrate, a gate line, first and second data lines, a first power line, first, second, third and fourth switching elements, and first, second, third and fourth pixel electrodes. The first switching element is connected to the gate line and the first data line. The second switching element is connected to the gate line and the first power line. The third switching element is connected to the gate line and the second data line. The fourth switching element is connected to the gate line and the first power line. The first to fourth pixel electrodes are connected to the first to fourth switching elements, respectively. Thus, a light leakage may be prevented and an aperture ratio of a display substrate may be enhanced.

Abstract translation: 液晶显示装置包括基板，栅极线，第一和第二数据线，第一电力线，第一，第二，第三和第四开关元件以及第一，第二，第三和第四像素电极。 第一开关元件连接到栅极线和第一数据线。 第二开关元件连接到栅极线和第一电力线。 第三开关元件连接到栅极线和第二数据线。 第四开关元件连接到栅极线和第一电力线。 第一至第四像素电极分别连接到第一至第四开关元件。 因此，可以防止漏光，并且可以提高显示基板的开口率。

公开(公告)号：US20100134399A1

公开(公告)日：2010-06-03

申请号：US12423995

申请日：2009-04-15

Applicant: Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

Inventor： Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

Abstract translation: 驱动栅极线的方法包括：将扫描开始信号和从前一级提供的进位信号中的一个充电到当前级的第一个节点; 通过在第一节点处拉高高电平的第一时钟信号，通过当前级的门节点输出门信号，以升高第一节点的电压电位; 当第一时钟信号被转换到低电平时，放电第一节点的电压和门节点的电压电位，以将第一节点和门节点保持在第一电源电压; 并且接收前一级的第二节点的电压电位信号，所述第二节点保持从前一级输出的门信号，以减少在第一节点处产生的纹波。

公开(公告)号：US20080100560A1

公开(公告)日：2008-05-01

申请号：US11928466

申请日：2007-10-30

Applicant: Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

Inventor： Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/041

Abstract: In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.

Abstract translation: 在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号 通过输出端子输出到栅极导通电压。 缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。 缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。 因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。

公开(公告)号：US20060177770A1

公开(公告)日：2006-08-10

申请号：US11303653

申请日：2005-12-15

Applicant: Jeong-il Kim ,  Dong-hyeon Ki ,  Yun-hee Kwak ,  Hyeong-jun Park ,  Byeong-jae Ahn ,  Shin-tack Kang

Inventor： Jeong-il Kim ,  Dong-hyeon Ki ,  Yun-hee Kwak ,  Hyeong-jun Park ,  Byeong-jae Ahn ,  Shin-tack Kang

IPC: G03C5/00

CPC classification number: H01L21/84 ,  H01L27/12

Abstract: The present invention relates to a thin film transistor (TFT) substrate and method of making such a TFT substrate. The structure of the TFT substrate helps prevent damage to signal lines in non-display areas.