公开(公告)号：US20080100560A1

公开(公告)日：2008-05-01

申请号：US11928466

申请日：2007-10-30

申请人： Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

发明人： Byoung-Sun NA ,  Dong-Hyeon KI ,  Min-Cheol LEE ,  Soon-Il AHN

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/041

摘要： In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.

摘要翻译： 在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号 通过输出端子输出到栅极导通电压。 缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。 缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。 因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。

公开(公告)号：US20100007653A1

公开(公告)日：2010-01-14

申请号：US12333561

申请日：2008-12-12

申请人： Soon-Il AHN ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Hyon KI ,  Seung-Soo BAEK ,  Hye-Seok NA

发明人： Soon-Il AHN ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Hyon KI ,  Seung-Soo BAEK ,  Hye-Seok NA

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3677 ,  G09G2330/08 ,  G11C19/184 ,  G11C19/28

摘要： A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

摘要翻译： 一种包括n个移位寄存器的栅极驱动器，其中n是等于或大于1的整数，n个移位寄存器中的每一个包括： 开始阶段，其响应于起始信号输出门信号并开始其操作;以及多个后续级，它们依次相互连接，并且响应于从...输出的信号顺序地输出多个门信号 起始阶段，其中多个后续级中的至少一级由起始信号复位。

公开(公告)号：US20080055292A1

公开(公告)日：2008-03-06

申请号：US11845285

申请日：2007-08-27

申请人： Hee-Wook DO ,  Byoung-Sun NA ,  Seung-Hoo YOO ,  Soon-Il AHN ,  Hyun-Cheol MOON ,  Hye-Ran YOU

发明人： Hee-Wook DO ,  Byoung-Sun NA ,  Seung-Hoo YOO ,  Soon-Il AHN ,  Hyun-Cheol MOON ,  Hye-Ran YOU

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G02F1/133707 ,  G02F1/13624 ,  G02F2001/134318 ,  G02F2001/134345 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0876

摘要： In a display panel, main and sub pixel electrodes are connected to first and second drain electrodes of a thin film transistor, respectively, to receive a data voltage during a 1 H period as main and sub pixel voltages. A main storage electrode overlaps the main pixel electrode to receive a first common voltage that varies with the gate pulse and the polarity of the data voltage. A sub storage electrode overlaps the sub pixel electrode to receive a second common voltage that is uniformly maintained at a constant voltage level. The sub pixel voltage is uniformly maintained by the second common voltage, but the main pixel voltage is shifted up or down by the first common voltage. Thus, the main pixel voltage may have a voltage level higher than that of the sub pixel voltage.

摘要翻译： 在显示面板中，主像素电极和子像素电极分别连接到薄膜晶体管的第一和第二漏电极，以在1H周期内接收数据电压作为主像素电压和子像素电压。 主存储电极与主像素电极重叠以接收随着栅极脉冲和数据电压的极性而变化的第一公共电压。 子存储电极与子像素电极重叠以接收均匀地保持在恒定电压电平的第二公共电压。 子像素电压由第二公共电压均匀地维持，但主像素电压被上下移动第一公共电压。 因此，主像素电压可以具有比子像素电压的电压电平更高的电压电平。

公开(公告)号：US20100134399A1

公开(公告)日：2010-06-03

申请号：US12423995

申请日：2009-04-15

申请人： Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

发明人： Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

摘要翻译： 驱动栅极线的方法包括：将扫描开始信号和从前一级提供的进位信号中的一个充电到当前级的第一个节点; 通过在第一节点处拉高高电平的第一时钟信号，通过当前级的门节点输出门信号，以升高第一节点的电压电位; 当第一时钟信号被转换到低电平时，放电第一节点的电压和门节点的电压电位，以将第一节点和门节点保持在第一电源电压; 并且接收前一级的第二节点的电压电位信号，所述第二节点保持从前一级输出的门信号，以减少在第一节点处产生的纹波。

公开(公告)号：US20090290114A1

公开(公告)日：2009-11-26

申请号：US12418873

申请日：2009-04-06

申请人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

发明人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707

摘要： A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented.

摘要翻译： 在显示基板和具有显示基板的垂直取向模式的显示面板上形成第一狭缝图案。 第一狭缝图案包括狭缝，一对突起和一对凹口。 狭缝在彼此相遇并且狭缝的切口部分的发散点在产生液晶的奇异点时具有与该对突起相同的功能。 在阵列基板的保护层上形成露出开关元件的输出电极的一部分的接触孔。 在对应于存储电极的保护层上形成台阶凹槽，狭缝的发散点被布置成对应于存储电极。 液晶的奇异点被诱发发生在规则位置，因此可以防止残影和斑点。

公开(公告)号：US20090114920A1

公开(公告)日：2009-05-07

申请号：US12351726

申请日：2009-01-09

申请人： Byoung-Sun NA

发明人： Byoung-Sun NA

IPC分类号： H01L27/088

CPC分类号： G02F1/133707 ,  G02F1/134336 ,  G02F1/1393

摘要： An LCD device includes a first substrate having a first base substrate, patterns disposed at different heights with respect to the first base substrate, and an insulation layer formed on the first base substrate and the patterns. The insulation layer has raised portions corresponding to the patterns. A side of the raised portions forms an inclination angle of no more than about 45° when a height of the raised portions is more than about 3000 angstroms, the side of the raised portions forms an inclination angle of no more than about 50° when a height of the raised portions is in a range of about 2000 angstroms to about 3000 angstroms, and the side of the raised portions forms an inclination angle of no more than about 90° when a height of the raised portions is more than about 2000 angstroms. Therefore, light leakage may be minimized.

摘要翻译： LCD装置包括具有第一基底基板的第一基板和相对于第一基底基板设置在不同高度的图案，以及形成在第一基底基板和图案上的绝缘层。 绝缘层具有对应于图案的凸起部分。 当凸起部分的高度大于约3000埃时，凸起部分的一侧形成不大于约45°的倾斜角，当a的高度大于约3000埃时，凸起部分的侧面形成不大于约50°的倾斜角度 凸起部分的高度在约2000埃至约3000埃的范围内，并且当凸起部分的高度大于约2000埃时，凸起部分的侧面形成不超过约90度的倾斜角。 因此，可以使光泄漏最小化。

公开(公告)号：US20120113375A1

公开(公告)日：2012-05-10

申请号：US13355398

申请日：2012-01-20

申请人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

发明人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707

摘要： A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented.

摘要翻译： 在显示基板和具有显示基板的垂直取向模式的显示面板上形成第一狭缝图案。 第一狭缝图案包括狭缝，一对突起和一对凹口。 狭缝在彼此相遇并且狭缝的切口部分的发散点在产生液晶的奇异点时具有与该对突起相同的功能。 在阵列基板的保护层上形成露出开关元件的输出电极的一部分的接触孔。 在对应于存储电极的保护层上形成台阶凹槽，狭缝的发散点被布置成对应于存储电极。 液晶的奇异点被诱发发生在规则位置，因此可以防止残影和斑点。

公开(公告)号：US20100208157A1

公开(公告)日：2010-08-19

申请号：US12507764

申请日：2009-07-22

申请人： Ji-Hyun KWON ,  Hey-Seok NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Yoon LEE ,  Ju-Hee LEE ,  Gwang-Bum KO

发明人： Ji-Hyun KWON ,  Hey-Seok NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Yoon LEE ,  Ju-Hee LEE ,  Gwang-Bum KO

IPC分类号： G02F1/1368 ,  G02F1/13

CPC分类号： G02F1/136286 ,  G02F1/134363 ,  G02F2001/134345 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2320/0209

摘要： A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a plurality of pixels arranged in a matrix shape. Each of the pixels include a first subpixel and a second subpixel. The pixels include a first thin film transistor transmitting a first data voltage to the first subpixel. The first thin film transistor includes a first source electrode, a first drain electrode, and a first gate electrode. The pixels include a second thin film transistor transmitting a second data voltage to the second subpixel. The second thin film transistor includes a second source electrode, a second drain electrode, and a second gate electrode. A relative position of the first drain electrode with respect to the first source electrode is opposite to a relative position of the second drain electrode with respect to the second source electrode in each pixel.

摘要翻译： 根据本发明的示例性实施例的液晶显示器（LCD）包括以矩阵形状排列的多个像素。 每个像素包括第一子像素和第二子像素。 像素包括向第一子像素发送第一数据电压的第一薄膜晶体管。 第一薄膜晶体管包括第一源电极，第一漏电极和第一栅电极。 像素包括向第二子像素传输第二数据电压的第二薄膜晶体管。 第二薄膜晶体管包括第二源电极，第二漏电极和第二栅电极。 第一漏电极相对于第一源电极的相对位置与第二漏电极相对于每个像素中的第二源电极的相对位置相反。

公开(公告)号：US20120181539A1

公开(公告)日：2012-07-19

申请号：US13161124

申请日：2011-06-15

申请人： Hye-Rim HAN ,  Byoung-Sun NA ,  Jae-Jin SONG ,  Hyung-Jun PARK ,  Si Hyun AHN ,  Woo-Jung SHIN

发明人： Hye-Rim HAN ,  Byoung-Sun NA ,  Jae-Jin SONG ,  Hyung-Jun PARK ,  Si Hyun AHN ,  Woo-Jung SHIN

IPC分类号： H01L29/786

CPC分类号： H01L27/124 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0267 ,  H01L27/0288

摘要： The present invention relates to a thin film transistor array panel including: a substrate; gate lines formed on the substrate; and a gate driver formed on the substrate to apply gate signals to the gate lines. The gate driver includes a first wire and a second wire to transmit different signals, and at least one of the first wire and the second wire includes a static electricity preventing structure to prevent static electricity from accumulating between the first wire and the second wire.

摘要翻译： 薄膜晶体管阵列技术领域本发明涉及一种薄膜晶体管阵列面板，包括：基板; 形成在基板上的栅极线; 以及形成在衬底上以将栅极信号施加到栅极线的栅极驱动器。 栅极驱动器包括第一线和第二线以传输不同的信号，并且第一线和第二线中的至少一个包括防静电结构，以防止静电积累在第一线和第二线之间。

公开(公告)号：US20110279358A1

公开(公告)日：2011-11-17

申请号：US12903463

申请日：2010-10-13

申请人： Kye-Uk LEE ,  Kee-Bum PARK ,  Byoung-Sun NA

发明人： Kye-Uk LEE ,  Kee-Bum PARK ,  Byoung-Sun NA

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2320/0223 ,  G11C19/28

摘要： An exemplary embodiment of a display panel according to the present invention includes; a substrate, a display area including a gate line disposed on the substrate, and a gate driver connected to one end of the gate line, the gate driver including a plurality of stages disposed in a first direction, and integrated on the substrate, wherein the gate driver includes; a plurality of clock signal lines extending in the first direction and a voltage signal line extending in the first direction, and the voltage signal line disposed between the plurality of clock signal lines and the plurality of stages.

摘要翻译： 根据本发明的显示面板的示例性实施例包括： 衬底，包括设置在衬底上的栅极线的显示区域和连接到栅极线的一端的栅极驱动器，栅极驱动器包括沿第一方向设置并集成在衬底上的多个级，其中， 门驱动器包括 沿第一方向延伸的多个时钟信号线和沿第一方向延伸的电压信号线，以及设置在多个时钟信号线与多个级之间的电压信号线。