Central processing unit with internal register initializing means
    31.
    发明授权
    Central processing unit with internal register initializing means 失效
    具有内部寄存器初始化手段的中央处理单元

    公开(公告)号:US5596761A

    公开(公告)日:1997-01-21

    申请号:US101399

    申请日:1993-08-02

    IPC分类号: G06F9/32 G06F9/38 G06F9/00

    CPC分类号: G06F9/3861 G06F9/32

    摘要: A central processing unit (CPU) carries out selected reset interruption processing by using a vector address preset in accordance with an interruption source to generate an address to a data table whose contents are used to initialize selected registers. In this manner, the CPU can be reset without having first stored the processing state of the CPU in response to a reset interrupt request, without the need for extensive dedicated reset hardware, and with the ability to select desired reset values that can differ as between different interrupts and can be changed from time to time.

    摘要翻译: 中央处理单元(CPU)通过使用根据中断源预设的向量地址来执行所选择的复位中断处理,以将内容生成到其内容用于初始化所选择的寄存器的数据表。 以这种方式,CPU可以被复位而不需要首先存储CPU的处理状态,而不需要广泛的专用复位硬件,并且具有选择期望的复位值的能力,所述复位值可以不同 不同的中断,可以不时更改。

    Central processing unit
    32.
    发明授权
    Central processing unit 失效
    中央处理器

    公开(公告)号:US5161229A

    公开(公告)日:1992-11-03

    申请号:US533383

    申请日:1990-06-05

    IPC分类号: G06F9/48 G06F9/38

    CPC分类号: G06F9/3861

    摘要: A central processing unit has a plurality of control sections; a device for selectively operating and unoperating the control sections by an external interrruption signal; and a device for processing an interruption sequence with respect to the interruption signal by the operations of the control sections in a state in which the control sections are operated. The control processing unit may be constructed such that the control sections are composed of two control sections and one of the two control sections processes a normal instruction sequence and is unoperated by the interruption signal, and the other of the two control sections is operated at the times of the normal instruction and interruption and processes the interruption sequence in addition to the normal instruction.

    摘要翻译: 中央处理单元具有多个控制部分; 用于通过外部中断信号选择性地操作和不操作所述控制部分的装置; 以及用于在控制部分被操作的状态下通过控制部分的操作来处理关于中断信号的中断序列的装置。 控制处理单元可以被构造成使得控制部分由两个控制部分组成,并且两个控制部分中的一个控制部分处理正常指令序列并且由中断信号进行未操作,并且两个控制部分中的另一个在 正常指令的次数和中断,并处理除了正常指令之外的中断序列。

    Motorcycle disc braking materials of a low carbon martensitic stainless
steel
    34.
    发明授权
    Motorcycle disc braking materials of a low carbon martensitic stainless steel 失效
    摩托车盘式制动材料的低碳马氏体不锈钢

    公开(公告)号:US4452649A

    公开(公告)日:1984-06-05

    申请号:US448901

    申请日:1982-12-03

    摘要: This invention belongs to the technical field of martensitic stainless steels and the moderate hardness, toughness and corrosion resistance required for motorcycle braking disc materials can be provided only by quenching at a broad range of quenching temperature by restraining the content of C+N in the steels to 0.04-0.10% and containing 1.0-2.5% of Mn and 10.0-14.5% of Cr.

    摘要翻译: PCT No.PCT / JP82 / 00210 Sec。 371日期1982年12月3日 102(e)1982年12月3日日期PCT提交1982年5月28日PCT公布。 出版物WO82 / 04268 日本1982年12月9日。本发明属于马氏体不锈钢的技术领域,摩托车制动盘材料所要求的适度的硬度,韧性和耐腐蚀性只能通过抑制内容物在宽范围的淬火温度下淬火来提供 的钢中的C + N为0.04-0.10%,含有1.0-2.5%的Mn和10.0-14.5%的Cr。

    Information processing apparatus and method, recording medium, and program
    36.
    发明授权
    Information processing apparatus and method, recording medium, and program 有权
    信息处理装置和方法,记录介质和程序

    公开(公告)号:US08683528B2

    公开(公告)日:2014-03-25

    申请号:US10522444

    申请日:2003-07-23

    IPC分类号: G06F3/00 G06F13/00 H04N5/445

    摘要: Information processing methods to make it possible to reserve recording of a program without imposing a large burden on a user. A server transmits program attribute information to a video recording and reproducing apparatus via a network. The program attribute information includes program attribute names and program attribute retrieval conditions. The video recording and reproducing apparatus causes a display apparatus to display a list of the program attribute names. The user selects from the list a program attribute name to which a program that the user wishes to reserve for recording seems to be most closely related. The video recording and reproducing apparatus compares the retrieval conditions corresponding to the selected program attribute name and EPG (electronic program guide) information and, when the retrieval conditions are satisfied, records a program represented by the EPG in a recording reservation list. The methods can be applied to a hard disk video recorder.

    摘要翻译: 信息处理方法,使得可以保留节目的记录而不对用户施加大的负担。 服务器通过网络将节目属性信息发送到视频记录和再现装置。 程序属性信息包括程序属性名和程序属性检索条件。 视频记录和再现装置使显示装置显示节目属性名称的列表。 用户从列表中选择节目属性名称,用户希望保留用于记录的节目似乎与之最相关。 视频记录和再现装置将与所选择的节目属性名称和EPG(电子节目指南)信息相对应的检索条件进行比较,并且当满足检索条件时,将由EPG表示的节目记录在记录预约列表中。 这些方法可以应用于硬盘录像机。

    Programmable logic array and data processing unit using the same
    39.
    发明授权
    Programmable logic array and data processing unit using the same 失效
    可编程逻辑阵列和数据处理单元使用相同

    公开(公告)号:US5511173A

    公开(公告)日:1996-04-23

    申请号:US177794

    申请日:1994-01-05

    CPC分类号: H03K19/1772 G06F9/223

    摘要: A programmable logic array includes a plurality of AND planes. Each AND plane executes an AND logic operation and has input terminals and output terminals. The programmable logic array also includes a single OR plane provided in common for the plurality of AND planes. The single OR plane executes an OR logic operation and has input terminals coupled to the output terminals of the plurality of AND planes and output terminals. A data processing unit using the above programmable logic array is also provided.

    摘要翻译: 可编程逻辑阵列包括多个AND平面。 每个AND平面执行AND逻辑运算,并具有输入端和输出端。 可编程逻辑阵列还包括为多个AND平面共同提供的单个OR平面。 单OR平面执行或逻辑运算,并且具有耦合到多个AND平面和输出端的输出端的输入端。 还提供了使用上述可编程逻辑阵列的数据处理单元。

    Standard cell circuit, semiconductor integrated circuit, and semiconductor integrated circuit device
    40.
    发明授权
    Standard cell circuit, semiconductor integrated circuit, and semiconductor integrated circuit device 有权
    标准单元电路,半导体集成电路和半导体集成电路器件

    公开(公告)号:US08829970B2

    公开(公告)日:2014-09-09

    申请号:US13556512

    申请日:2012-07-24

    IPC分类号: H03L5/00

    摘要: A standard cell circuit including an input terminal to which input an input signal is input; an output terminal to output an output signal; a first wiring conductor, connected to an external power supply that outputs a first power supply voltage; a second wiring conductor to supply a second power supply voltage that is lower than the first power supply voltage; a standard cell to operate at the second power supply voltage supplied from the second wiring conductor; and a conversion circuit, connected to the first wiring conductor and the second wiring conductor, to convert the first power supply voltage input from the first wiring conductor into the second power supply voltage for output to the second wiring conductor.

    摘要翻译: 一种标准单元电路,包括:输入端输入输入信号的输入端子; 输出端子,输出输出信号; 连接到输出第一电源电压的外部电源的第一布线导体; 第二布线导体,用于提供低于第一电源电压的第二电源电压; 在从所述第二布线导体提供的所述第二电源电压下工作的标准单元; 以及转换电路,连接到第一布线导体和第二布线导体,以将从第一布线导体输入的第一电源电压转换为第二电源电压,以输出到第二布线导体。