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公开(公告)号：US20210303390A1
公开(公告)日：2021-09-30
申请号：US17216640
申请日：2021-03-29
发明人： Hiroji AKAHORI
摘要： To provide a semiconductor device having a monitoring function with a higher degree of freedom. The semiconductor device includes: a function part that executes a predetermined process triggered according to an activation signal sent from an external device and outputs a completion signal after the predetermined process is completed; a first clocking part that monitors a first abnormality in the predetermined process based on the activation signal and the completion signal; and a branch part pair including a first branch part and a second branch part, wherein the first branch part branches the activation signal and then sends the branched activation signal to the function part and the first clocking part, and the second branch part branches the completion signal and then sends the branched completion signal to the first clocking part and the external device.
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公开(公告)号：US20210302724A1
公开(公告)日：2021-09-30
申请号：US17215981
申请日：2021-03-29
发明人： Yuki IMATOH
摘要： An image distortion correction circuit performs a distortion correction process on an image signal on the basis of distortion correction data to generate a distortion-corrected image signal. The distortion correction data is for correcting coordinate positions of display data fragments corresponding to respective N coordinate positions in the display image to first to N-th distortion correction coordinate positions. The image distortion correction circuit determines a distortion correction coordinate position where abnormality occurs as an abnormal coordinate position among the first to N-th distortion correction coordinate positions on the basis of respective intervals between the adjacent first to N-th distortion correction coordinate positions indicated by the distortion correction data. The image distortion correction circuit corrects a part corresponding to the abnormal coordinate position in the distortion correction data on the basis of at least the two distortion correction coordinate positions excluding the abnormal coordinate position among the first to N-th distortion correction coordinate positions.
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公开(公告)号：US11127439B2
公开(公告)日：2021-09-21
申请号：US16823314
申请日：2020-03-18
发明人： Kenjiro Matoba
摘要： A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
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公开(公告)号：US20210270636A1
公开(公告)日：2021-09-02
申请号：US17185914
申请日：2021-02-25
发明人： Hiroji AKAHORI
摘要： An average processing section, a timer, and a control section are provided. The average processing section is configured to compute an average measurement value, this being an average value of plural observed values of each of plural measurement targets as output from a switching section that switches output between measurement values acquired from each of the plural measurement targets. The timer is configured to generate a timer signal configured by timing signals at a predetermined interval. The control section is configured to control the switching section and the average processing section so as to compute the average measurement value for each of the measurement targets according to the timer signal and according to a measurement sequence to set an order of measurement and a number of measurements for the plural measurement targets.
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公开(公告)号：US11100869B2
公开(公告)日：2021-08-24
申请号：US16660782
申请日：2019-10-22
发明人： Akira Nakayama
IPC分类号： G09G3/3291 , G09G3/3233 , G09G3/20 , G09G3/3266
摘要： A semiconductor apparatus including a driver capable of favorably suppressing image deterioration accompanying a voltage fluctuation even if the voltage fluctuation is generated in a display device is provided. The semiconductor apparatus of the disclosure includes: a gradation voltage generation portion generating a first to kth representative gradation voltage in accordance with gamma characteristics and generating a first to Nth gradation voltage based on the first to kth representative gradation voltage; a driving portion selecting one gradation voltage corresponding to display data from the first to Nth gradation voltage and applying a signal representing the selected one gradation voltage as a driving signal to source lines; and a fluctuating voltage superposition portion generating, when a voltage fluctuation is generated in the power supply voltage for making display cells emit light, a voltage fluctuation corresponding to the voltage fluctuation in at least one of the first to kth representative gradation voltage.
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公开(公告)号：US20210241711A1
公开(公告)日：2021-08-05
申请号：US17164904
申请日：2021-02-02
发明人： Daisei NAGATA
IPC分类号： G09G3/36
摘要： A display device has: a display panel; a source driver group including 2j source drivers that are arranged in the lengthwise direction of gate lines; and a display controller that is connected to the 2j source drivers via j data supply lines provided in common between adjacent pairs of source drivers. The display controller outputs j pixel data piece groups, into which m/2 pixel data pieces were divided, to the data supply lines. The (2k)th source driver receives m/(4j) pixel data pieces via a data supply line, and receives three pixel data pieces from the (2k+1)th source driver. The (2k)th source driver generates m/(2j) of gradation voltage signals on the basis of the pixel data pieces.
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公开(公告)号：US11075626B2
公开(公告)日：2021-07-27
申请号：US16799133
申请日：2020-02-24
发明人： Seiichiro Sasaki
摘要： A power-on clear circuit includes a bias current generation circuit having one end connected to a first line supplied with a first power supply voltage, the other end connected to a second line kept at a fixed potential, and configured to generate a bias current, and to transmit the bias current to a first node; a first transistor having a first terminal connected to the second line, a second terminal connected to the first node, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; an inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of the first node is input; and a signal outputting unit configured to output a power-on clear signal in accordance with an output of the inverter unit.
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公开(公告)号：US11073496B2
公开(公告)日：2021-07-27
申请号：US16171631
申请日：2018-10-26
发明人： Kazuhiro Nakano
IPC分类号： G01N27/414 , G01N27/30
摘要： A reference electrode including a casing through which one face at one side of a liquid junction that leaches an internal liquid is exposed. The casing is provided with an overhang portion that hangs out on the one face side of the liquid junction and prevents separation of the liquid junction from the casing; and an open portion that leaves a space on the one side of the liquid junction open toward a lateral direction along the one face.
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公开(公告)号：US11049826B2
公开(公告)日：2021-06-29
申请号：US15869713
申请日：2018-01-12
发明人： Taiichi Ogumi
IPC分类号： H01L23/00 , H01L25/065
摘要： A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.
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公开(公告)号：US11009904B2
公开(公告)日：2021-05-18
申请号：US16941738
申请日：2020-07-29
发明人： Kenjiro Matoba , Kazuhiro Yamashita
IPC分类号： G06F1/04 , H03K19/0185
摘要： An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
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