公开(公告)号：US08447962B2

公开(公告)日：2013-05-21

申请号：US12644440

申请日：2009-12-22

申请人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

发明人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3865

摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

公开(公告)号：US20120166761A1

公开(公告)日：2012-06-28

申请号：US12976616

申请日：2010-12-22

申请人： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

发明人： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

IPC分类号： G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

摘要翻译： 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：US06418525B1

公开(公告)日：2002-07-09

申请号：US09240348

申请日：1999-01-29

申请人： Mark J. Charney ,  Philip G. Emma ,  Daniel A. Prener ,  Thomas R. Puzak

发明人： Mark J. Charney ,  Philip G. Emma ,  Daniel A. Prener ,  Thomas R. Puzak

IPC分类号： G06F1208

CPC分类号： G06F9/3806 ,  G06F9/30047 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： A method and apparatus for storing and utilizing set prediction information regarding which set of a set-associative memory will be accessed for enhancing performance of the set-associative memory and reducing power consumption. The set prediction information is stored in various locations including a branch target buffer, instruction cache and operand history table to decrease latency for accesses to set-associative instruction and data caches.

摘要翻译： 一种用于存储和利用关于将被访问哪组集合关联存储器的集合预测信息以增强集合关联存储器的性能并降低功耗的方法和装置。 设定的预测信息被存储在包括分支目标缓冲器，指令高速缓存和操作数历史表的各种位置中，以减少对设置关联指令和数据高速缓存的访问的等待时间。

公开(公告)号：US10564966B2

公开(公告)日：2020-02-18

申请号：US13977171

申请日：2011-12-22

申请人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed Vall ,  Mark J. Charney

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Elmoustapha Ould-Ahmed Vall ,  Mark J. Charney

IPC分类号： G06F9/30

摘要： A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US10114651B2

公开(公告)日：2018-10-30

申请号：US15862407

申请日：2018-01-04

申请人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

发明人： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC分类号： G06F9/00 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30

摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US20180129506A1

公开(公告)日：2018-05-10

申请号：US15862407

申请日：2018-01-04

申请人： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

发明人： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US20170192780A1

公开(公告)日：2017-07-06

申请号：US14984078

申请日：2015-12-30

申请人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

发明人： Robert Valentine ,  Elmoustapha Ould-Ahmed-Vall ,  Jason W. Brandt ,  Mark J. Charney ,  Ashish Jha ,  Milind B. Girkar ,  Bret L. Toll ,  Evgeny V. Stupachenko ,  Sergey Y. Ostanevich

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30192

摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.

公开(公告)号：US09513918B2

公开(公告)日：2016-12-06

申请号：US13995974

申请日：2011-12-22

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mostafa Hagog ,  Jesus Corbal ,  Bret L Toll ,  Mark J Charney ,  Tal Uliel ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30196 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3867

摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.

摘要翻译： 描述了用掩模来置换数据元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个 可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。

公开(公告)号：US09424327B2

公开(公告)日：2016-08-23

申请号：US13976433

申请日：2011-12-23

申请人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney

IPC分类号： G06F7/00 ,  G06F17/30 ,  G06F9/30

CPC分类号： G06F21/6227 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3802 ,  G06F17/30575 ,  G06F21/6254 ,  G06F21/70

摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.

摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，以在执行第一指令时存储待复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 当执行第一指令以创建第一复制数据结构时，执行单元还包括复制第一数据结构的复制逻辑电路，以及在执行第二数据指令以创建第二复制数据结构时复制第二数据结构。 执行单元还包括掩蔽逻辑电路，以第一粒度掩蔽第一复制数据结构，并以第二粒度掩蔽第二复制数据结构。 第二粒度是第一粒度的两倍。

公开(公告)号：US20160179539A1

公开(公告)日：2016-06-23

申请号：US14580069

申请日：2014-12-22

申请人： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  MARK J. CHARNEY

发明人： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  MARK J. CHARNEY

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3013

摘要： A processing device implements a set of instructions to perform a centrifuge operation using vector or general purpose registers. In one embodiment, the centrifuge operation separates bits in a source register to opposing regions of a destination register based on a control mask, where each source register bit with a corresponding control mask value of one is written to one region in a destination register, while source register bits with a corresponding control mask value of zero are written to an opposing region of the destination register.

摘要翻译： 处理装置实现一组指令以使用向量或通用寄存器执行离心机操作。 在一个实施例中，离心机操作基于控制掩模将源寄存器中的位分离到目标寄存器的相对区域，其中具有对应控制掩码值为1的每个源寄存器位被写入目的地寄存器中的一个区域，而 具有对应控制掩码值为零的源寄存器位被写入到目标寄存器的相对区域。