公开(公告)号：US20050188340A1

公开(公告)日：2005-08-25

申请号：US11079292

申请日：2005-03-15

申请人： Sadami Takeoka

发明人： Sadami Takeoka

IPC分类号： G01R31/3185 ,  G06F17/50

CPC分类号： G01R31/318586

摘要： A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

摘要翻译： 一种设计半导体集成电路的方法包括以下步骤：选择要作为扫描链连接的一对扫描寄存器，并计算硬件上从前级扫描寄存器的每个输出端到扫描数据输入端的扫描数据输入端 后级扫描寄存器。 该方法还包括以下步骤：基于上述计算，在具有最小直线距离的前级选择扫描寄存器的输出端; 确定将所选输出端与后级扫描寄存器的扫描数据输入端连接; 以及通过使用在前一步骤中确定的输出端子连接每对扫描寄存器来形成扫描链。

公开(公告)号：US06708301B1

公开(公告)日：2004-03-16

申请号：US09381377

申请日：1999-09-20

申请人： Mitsuyasu Ohta ,  Sadami Takeoka ,  Toshihiro Hiraoka

发明人： Mitsuyasu Ohta ,  Sadami Takeoka ,  Toshihiro Hiraoka

IPC分类号： G01R3128

CPC分类号： H01L27/0207 ,  G06F11/2273

摘要： A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5).

摘要翻译： 半导体集成电路（1）包括第一，第二和第二功能块（10,20和30）。 第一，第二和第二功能块（10,20和30）通过块间信号线（2）耦合在一起。 第一功能块（10）包括：逻辑电路（11）; 测试数据输出电路（12），其在测试期间操作并输出预定的测试数据模式; 测试待机电路（14），其连接在选择器（13）和外部双向引脚之间，并使功能块在测试期间进入待机状态; 由测试待机电路（14）使其具有高阻抗的三态缓冲器（15）; 以及从第二功能块接收测试数据模式的判定结果输出电路（16）将接收到的测试数据模式与存储在其中的期望值进行比较，并将判定结果输出到判定结果信号线（5）。

公开(公告)号：US06427218B2

公开(公告)日：2002-07-30

申请号：US09725264

申请日：2000-11-29

申请人： Sadami Takeoka

发明人： Sadami Takeoka

IPC分类号： G06F1100

CPC分类号： G01R31/318392

摘要： A method of generating a test pattern for a semiconductor integrated circuit including a logic circuit containing a combinational logic element, a first sequential circuit having an output side connected to an input side of the logic circuit, and a second sequential circuit having an input side connected to an output side of the logic circuit, whereby a test pattern for testing a signal path between the first and second sequential circuits for a data retention error associated with data held by the second sequential circuit based on output data of the second sequential circuit is generated. To generate the test pattern, a first test pattern is generated by setting, at the first sequential circuit, a first set value for the signal path such that the signal path is activated immediately before and after one pulse of a clock signal for synchronization is inputted and a second test pattern is generated by setting, at the first sequential circuit, a second set value obtained by inverting the first set value.

摘要翻译： 一种生成用于半导体集成电路的测试图形的方法，该半导体集成电路包括包含组合逻辑元件的逻辑电路，具有连接到逻辑电路的输入侧的输出端的第一时序电路和连接有输入端的第二时序电路 到达逻辑电路的输出侧，由此产生用于测试第一和第二顺序电路之间的信号路径的测试图案，用于基于第二顺序电路的输出数据与由第二顺序电路保持的数据相关联的数据保持错误 。 为了产生测试图案，通过在第一顺序电路处设置信号路径的第一设定值来产生第一测试图案，使得信号路径在输入用于同步的时钟信号的一个脉冲之前和之后立即被激活 并且通过在第一顺序电路处设置通过反转第一设定值而获得的第二设定值来生成第二测试图案。

公开(公告)号：US06205566B1

公开(公告)日：2001-03-20

申请号：US09119589

申请日：1998-07-21

申请人： Sadami Takeoka

发明人： Sadami Takeoka

IPC分类号： G01R3128

CPC分类号： G01R31/318552

摘要： In a semiconductor integrated circuit, a select signal output circuit switches a selector to take in the output of a circuit section in response to a signal “0” received at the D terminal thereof during normal operation. Thus, a scan flip-flop receives the output of the circuit section. During a scan test mode, a select signal “0” or “1” is input through a scan-in terminal to the select signal output circuit and then to the selector. If the select signal is “0”, then the selector selects the output of the circuit section. On the other hand, if the select signal is “1”, then the selector selects a clock signal supplied from a clock signal generator. The output of the circuit section or the clock signal supplied from the clock signal generator, which has been input to the scan flip-flop, is passed through a scan path and output to the outside through a scan-out terminal. As a result, an internally formed clock signal generator or the like can be tested easily.

摘要翻译： 在半导体集成电路中，选择信号输出电路响应于在正常操作期间在其D端接收到的信号“0”，切换选择器以接收电路部分的输出。 因此，扫描触发器接收电路部分的输出。 在扫描测试模式期间，选择信号“0”或“1”通过扫描输入端输入到选择信号输出电路，然后输入到选择器。 如果选择信号为“0”，则选择器选择电路部分的输出。 另一方面，如果选择信号为“1”，则选择器选择从时钟信号发生器提供的时钟信号。 已经输入到扫描触发器的从时钟信号发生器提供的电路部分的输出或时钟信号通过扫描路径并通过扫描输出端输出到外部。 结果，可以容易地测试内部形成的时钟信号发生器等。