公开(公告)号：US5577219A

公开(公告)日：1996-11-19

申请号：US236587

申请日：1994-05-02

Applicant: Mark Timko ,  Scott D. Rodgers

Inventor： Mark Timko ,  Scott D. Rodgers

IPC: G06F9/355 ,  G06F12/14 ,  G06F12/06

CPC classification number: G06F9/355 ,  G06F12/1441

Abstract: A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.

Abstract translation: 一种用于确定计算机处理器中的存储器访问的有效地址是否在扩展下降存储器段之上的方法和装置。 该装置包括存储器段极限比较电路。 段限制比较电路测试每个存储器访问以确定存储器访问是否达到扩展存储器段的上限以上。 比较电路由加法器组成，该加法器将存储器访问的有效地址添加到访问大小值。 访问大小值包括要执行的存储器访问的大小减去低位中的一个，并且如果存储器访问达到上限以上，则生成进位所需的高位中的一系列“1”位 的扩展内存段。

公开(公告)号：US5517657A

公开(公告)日：1996-05-14

申请号：US220693

申请日：1994-03-30

Applicant: Scott D. Rodgers ,  Kamla P. Huck

Inventor： Scott D. Rodgers ,  Kamla P. Huck

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/00

CPC classification number: G06F9/3885 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3867 ,  G06F9/3875

Abstract: A mechanism and procedure for providing an efficient pipeline for reading and writing information to a multiple ported segment register file (SRF) in different pipestages. The present invention is operable, in one embodiment, within an address generation unit (AGU) of a processor and is implemented to write the SRF during a particular clock phase of a pipestage and to read to the SRF during another clock phase of another pipestage of the AGU pipeline of a pipelined processor. The read and write of different pipestages associated with separate instructions may occur within a same clock cycle. The write occurs before the read. By reading and writing to the AGU in alternate clock phases, the read and write operations of the SRF do not conflict even though they span different pipestages of the pipeline. Therefore, pipestages of the present invention are not in resource conflict over the SRF read and write operations which occur in a same clock cycle. Specifically, within the scope of the present invention, the SRF may be read during the low phase of a clock cycle while the SRF may be written during the high phase of a clock cycle for different instructions. Alternatively, the above phase relationships may be inverted.

Abstract translation: 一种用于在不同管道中为多端口段寄存器文件（SRF）读取和写入信息的有效管道的机制和过程。 本发明在一个实施例中可在处理器的地址生成单元（AGU）内操作，并且被实现为在分支的特定时钟相位期间写入SRF，并且在另一个分支的另一个时间段期间读取到SRF 流水线处理器的AGU管道。 与单独指令相关联的不同管道的读取和写入可以在相同的时钟周期内进行。 写入发生在读取之前。 通过在备用时钟阶段读取和写入AGU，SRF的读取和写入操作即使跨越管道的不同管道也不会发生冲突。 因此，在相同的时钟周期中发生的SRF读和写操作，本发明的分支管理不是资源冲突的。 具体地说，在本发明的范围内，可以在时钟周期的低相位期间读取SRF，同时可以在针对不同指令的时钟周期的高相位期间写入SRF。 或者，上述相位关系可以反转。