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公开(公告)号：US09645671B2
公开(公告)日：2017-05-09
申请号：US14958761
申请日：2015-12-03
Inventor： Kerui Xi , Zhaokeng Cao
CPC classification number: G06F3/0416 , G06F3/0412 , G06F3/044 , G06F3/046
Abstract: Array substrate, display panel and display device are provided. The array substrate includes: N sensor units; N signal detection terminals; a first control signal terminal; and a reference signal terminal, wherein ith sensor unit comprises inductor, capacitor and first switch transistor, first terminal of inductor and first polar plate of capacitor are connected with ith signal detection terminal, second terminal of inductor is connected with first terminal of first switch transistor, second polar plate of capacitor and second terminal of first switch transistor are connected with reference signal terminal, control terminal of first switch transistor is connected with first control signal terminal, during capacitive touch control stage, first switch transistor is turned off, and ith signal detection terminal outputs a capacitive detection signal; during inductive touch control stage, first switch transistor is turned on, and ith signal detection terminal outputs inductive detection signal. Thickness of the display device is reduced.
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公开(公告)号：US20170097713A1
公开(公告)日：2017-04-06
申请号：US15383790
申请日：2016-12-19
Inventor： Huijun Jin
IPC: G06F3/041 , G02F1/1339 , G02F1/1333 , G06F3/047
CPC classification number: G06F3/0412 , G02F1/13338 , G02F1/1339 , G02F2202/28 , G06F3/0416 , G06F2203/04103
Abstract: An array substrate and a display apparatus are provided. The array substrate includes a display area and a non-display area surrounding the display area, wherein the non-display area includes a frame sealing adhesive area, a plurality of touch leads and a plurality of touch signal output terminals. The plurality of touch signal output terminals are electrically connected with the plurality of touch leads, respectively, and the plurality of touch signal output terminals input a touch signal to the display area via the touch lead. A minimum distance between two adjacent touch leads in the frame sealing adhesive area is greater than a minimum distance between two adjacent touch signal output terminals correspondingly connected to said two adjacent touch leads.
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33.发明申请公开(公告)号：US20170061862A1
公开(公告)日：2017-03-02
申请号：US15352578
申请日：2016-11-16
Inventor： Dongliang Dun
IPC: G09G3/20
CPC classification number: G06F3/1446 , G09G2300/026 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
Abstract: A bidirectional scanning unit, a driving method and a gate driving circuit are provided. The bidirectional scanning unit includes a first-stage sub unit and a second-stage sub unit, the bidirectional scanning unit can output a scanning signal stage by stage in a direction from the first-stage sub unit to the second-stage sub unit, and can also output a scanning signal stage by stage in a direction from the second-stage sub unit to the first-stage sub unit. The first-stage sub unit coordinates with the second-stage sub unit in a scanning process, when one of the first-stage sub unit and the second-stage sub unit outputs the scanning signal, the other of the first-stage sub unit and the second-stage sub unit does not output the scanning signal.
Abstract translation: 提供双向扫描单元，驱动方法和栅极驱动电路。 双向扫描单元包括第一级子单元和第二级子单元，双向扫描单元可以在从第一级子单元到第二级子单元的方向上逐级输出扫描信号，以及 也可以在从第二级子单元到第一级子单元的方向逐级地输出扫描信号。 第一级子单元在扫描处理中与第二级子单元协调，当第一级子单元和第二级子单元之一输出扫描信号时，第一级子单元中的另一个子单元和 第二级子单元不输出扫描信号。
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公开(公告)号：US20160307938A1
公开(公告)日：2016-10-20
申请号：US15006643
申请日：2016-01-26
Inventor： HUIJUN JIN
IPC: H01L27/12
CPC classification number: H01L27/1255 , H01L27/1214 , H01L27/1225 , H01L27/124
Abstract: A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of bottom-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also includes a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality pre-reserved blank regions are configured among the scan lines, the data lines and the plurality of sub-pixels; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.
Abstract translation: 提供薄膜晶体管（TFT）阵列基板。 薄膜晶体管（TFT）阵列基板包括至少具有显示区域的基板; 以及形成在所述基板上的多个底栅型薄膜晶体管。 薄膜晶体管（TFT）阵列基板还包括在显示区域中形成在基板上的多条扫描线和多条数据线，并且限定多个子像素，其中多个预留空白区域被配置 在扫描线之间，数据线和多个子像素; 以及栅极驱动器电路，其形成在显示区域中的衬底上并且布置在显示区域中的预留空白区域中。
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公开(公告)号：US20160307937A1
公开(公告)日：2016-10-20
申请号：US15003792
申请日：2016-01-21
Inventor： HUIJUN JIN
IPC: H01L27/12
CPC classification number: H01L27/1255 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L29/78696
Abstract: A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of top-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also comprises a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality of pre-reserved blank regions are configured among the scan lines, the data lines, and the plurality of sub-pixels in the display region; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.
Abstract translation: 提供薄膜晶体管（TFT）阵列基板。 薄膜晶体管（TFT）阵列基板包括至少具有显示区域的基板; 以及形成在基板上的多个顶栅薄膜晶体管。 薄膜晶体管（TFT）阵列基板还包括在显示区域中形成在基板上并且限定多个子像素的多条扫描线和多条数据线，其中多个预留空白区域是 配置在显示区域中的扫描线，数据线和多个子像素之间; 以及栅极驱动器电路，其形成在显示区域中的衬底上并且布置在显示区域中的预留空白区域中。
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Patent Agency Ranking
公开(公告)号：US20160293270A1
公开(公告)日：2016-10-06
申请号：US15048792
申请日：2016-02-19
Inventor： Huijun Jin
CPC classification number: G11C19/287 , G06F3/0412 , G06F3/0416 , G06F3/047 , G06F2203/04103
Abstract: An array substrate and a method for forming the same are provided. The array substrate includes: a gate driver in a non-display area, wherein the gate driver includes M shift register circuits and each shift register circuit includes two shift register groups, which includes N shift registers each, where M is a positive even number and N is a positive integer greater than 2; in each of the shift register groups, a gate output end of an nth shift register has signal wires; along a direction perpendicular to the non-display area, at least one of the signal wires of one shift register group are stacked above at least one of the signal wires of another shift register group. Accordingly, a display panel using this array substrate may realize a narrow side frame design.
Abstract translation: 提供阵列基板及其形成方法。 阵列基板包括：非显示区域中的栅极驱动器，其中栅极驱动器包括M个移位寄存器电路，并且每个移位寄存器电路包括两个移位寄存器组，每个移位寄存器组包括N个移位寄存器，其中M是正偶数， N是大于2的正整数; 在每个移位寄存器组中，第n移位寄存器的栅极输出端具有信号线; 沿着垂直于非显示区域的方向，将一个移位寄存器组的信号线中的至少一个堆叠在另一个移位寄存器组的信号线中的至少一个之上。 因此，使用该阵列基板的显示面板可以实现窄边框设计。
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37.发明申请PIXEL STRUCTURE, ARRAY SUBSTRATE, DISPLAY PANEL, DISPLAY DEVICE, AND DRIVING METHOD OF DISPLAY DEVICE 有权像素结构，阵列基板，显示面板，显示设备以及显示设备的驱动方法公开(公告)号：US20160104447A1
公开(公告)日：2016-04-14
申请号：US14743941
申请日：2015-06-18
Inventor： Yao Lin , Zhaokeng Cao , Dandan Qin , Shoufu Jian , Tinghai Wang , Yinghua Mo
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3614
Abstract: A pixel structure, array substrate, display panel, display device, and driving method of the display device are provided. The pixel structure includes a plurality of data lines and a plurality of scan lines; a plurality of pixel units formed by intersecting the data lines with the scan lines. Each of the pixel units corresponds to one of the data lines and one of the scan lines; and the pixel unit includes a pixel electrode and a thin film transistor therein. In one of two adjacent columns of pixel units, a pixel electrode of each pixel unit is electrically connected with a thin film transistor of the pixel unit; and in the other one of the two adjacent columns of pixel units, a pixel electrode of each pixel unit in a row is electrically connected with a thin film transistor of a pixel unit in an adjacent row.
Abstract translation: 提供了像素结构，阵列基板，显示面板，显示装置以及显示装置的驱动方法。 像素结构包括多条数据线和多条扫描线; 通过将数据线与扫描线交叉而形成的多个像素单元。 每个像素单元对应于数据线之一和扫描线之一; 并且像素单元包括像素电极和薄膜晶体管。 在像素单元的两个相邻列之一中，每个像素单元的像素电极与像素单元的薄膜晶体管电连接; 并且在两个相邻列的像素单元中的另一个中，一行中的每个像素单元的像素电极与相邻行中的像素单元的薄膜晶体管电连接。
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公开(公告)号：US12107101B2
公开(公告)日：2024-10-01
申请号：US17546740
申请日：2021-12-09
Inventor： Kerui Xi , Xuhui Peng , Feng Qin , Tingting Cui , Zhenyu Jia
IPC: H01L27/146 , H01L25/16
CPC classification number: H01L27/14618 , H01L25/167 , H01L27/1462 , H01L27/14627 , H01L27/14636
Abstract: The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.
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公开(公告)号：US20230137800A1
公开(公告)日：2023-05-04
申请号：US18090918
申请日：2022-12-29
Inventor： Xuhui PENG , Kerui XI , Tingting CUI , Feng QIN , Jie ZHANG
IPC: H01L21/48 , H01L21/56 , H01L23/498 , H01L23/00
Abstract: A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.
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40.发明授权公开(公告)号：US11581196B2
公开(公告)日：2023-02-14
申请号：US16913020
申请日：2020-06-26
Inventor： Xuhui Peng , Kerui Xi , Tingting Cui , Feng Qin , Jie Zhang
IPC: H01L21/48 , H01L21/56 , H01L23/498 , H01L23/00
Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.
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