公开(公告)号：US20050041520A1

公开(公告)日：2005-02-24

申请号：US10920249

申请日：2004-08-18

Applicant: Hiroyuki Takahashi ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takuya Hirota

IPC: G11C8/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C11/40603 ,  G11C8/18 ,  G11C11/406

Abstract: A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

Abstract translation: 适于避免用于刷新的字线的选择周期与用于读/写的字线的选择周期之间的冲突的半导体存储器件包括包括需要刷新以保持存储的多个存储器单元的单元阵列 用于执行控制的数据和装置，使得当在执行刷新操作的时钟周期之后的时钟周期中输入读/写请求时，单元阵列中的读/写操作被延迟至少一个时钟周期，并且 读/写操作在完成刷新后开始。