公开(公告)号：US20160283438A1

公开(公告)日：2016-09-29

申请号：US15038710

申请日：2013-12-23

Applicant: Hu Tiger CHEN ,  Liang CHEN ,  Chunxiao LIN ,  Sai LUO ,  Hai Ge TIAN ,  Rui Gang WANG ,  Tin Fook NGAI ,  INTEL CORPORATION

Inventor： Hu Tiger CHEN ,  Liang CHEN ,  Chunxiao LIN ,  Sai LUO ,  Hai Ge TIAN ,  Rui Gang WANG ,  Tin-Fook NGAI

IPC: G06F15/80 ,  G06F13/40

CPC classification number: G06F15/80 ,  G06F13/4027 ,  G06F13/4068 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A processing device includes a first processor module comprising a first core designed according to a first instruction set (ISA), and a second processor module comprising a second core designed according to a second ISA. The first and second processor modules are fabricated on a same die.

Abstract translation: 一种处理装置包括：第一处理器模块，包括根据第一指令集（ISA）设计的第一核心;以及第二处理器模块，包括根据第二ISA设计的第二核心。 第一和第二处理器模块被制造在相同的芯片上。

公开(公告)号：US20140089634A1

公开(公告)日：2014-03-27

申请号：US13995490

申请日：2011-12-23

Applicant: Victor W. Lee ,  Daehyun Kim ,  Tin-Fook Ngai ,  Jayashankar Bharadwaj ,  Albert Hartono ,  Sara S. Baghsorkhi ,  Nalini Vasudevan

Inventor： Victor W. Lee ,  Daehyun Kim ,  Tin-Fook Ngai ,  Jayashankar Bharadwaj ,  Albert Hartono ,  Sara S. Baghsorkhi ,  Nalini Vasudevan

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30145

Abstract: An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register.

Abstract translation: 描述了用于识别向量寄存器中的相同元件的装置，系统和方法。 例如，根据一个实施例的计算机实现的方法包括以下操作：从第一向量寄存器读取每个活动元件，每个有源元件在第一向量寄存器内具有定义的位位置; 从第二向量寄存器读取每个元素，每个元素在第二向量寄存器内具有对应于第一向量寄存器中当前有效元素的位位置的定义的位位置; 读取输入掩码寄存器，所述输入掩码寄存器识别所述第二向量寄存器中的活动位位置，用于与所述第一向量寄存器中的值进行比较，所述比较操作包括：将所述第二向量寄存器中的每个有效元素与元素 在第一矢量寄存器中，位于第二向量寄存器中当前有效元件的位位置之前的位位置; 并且如果第一向量寄存器中的所有先前位位置等于第二向量寄存器中的当前活动位位置中的位，则将输出屏蔽寄存器中的位位置设置为等于真值。

公开(公告)号：US07770162B2

公开(公告)日：2010-08-03

申请号：US11321816

申请日：2005-12-29

Applicant: Li Liu ,  Zhaohui Du ,  Bu Qi Cheng ,  Shiwei Liao ,  Gansha Wu ,  Tin-fook Ngai

Inventor： Li Liu ,  Zhaohui Du ,  Bu Qi Cheng ,  Shiwei Liao ,  Gansha Wu ,  Tin-fook Ngai

IPC: G06F9/45

CPC classification number: G06F8/452

Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.

Abstract translation: 用于语句移位以增加循环并行性的方法包括构建数据依赖图（DDG）以表示循环中的语句之间的依赖关系，从DDG构建基本方程组，构建部分基本方程式导出的依赖方程组 并且从所述依赖方程组确定所述循环的移动向量，其中所述移位向量表示要应用于所述循环中用于语句移位的每个语句的偏移量。 还公开了其他实施例。