公开(公告)号：US12101609B1

公开(公告)日：2024-09-24

申请号：US18445647

申请日：2023-12-09

Applicant: Mohammad A. Mazed

Inventor： Mohammad A. Mazed

IPC: H04R3/00 ,  G06F15/78

CPC classification number: H04R3/00 ,  G06F15/7807 ,  H04R2420/07

Abstract: An intelligent (self-learning) subsystem comprising (i) a Super System on Chip (SSoC) (non-optically enabled or optically enabled) and/or a System-on-a-Chip (SoC), (ii) a radio transceiver, (iii) a microphone, (iv) a voice processing module, (v) a first set of computer implementable instructions to interpret/analyze contextual data and (vi) a second set of computer implementable instructions in artificial neural networks (ANN) (which can include a transformer model or a diffusion model and may also be augmented with an evolutionary instructions) is disclosed.

公开(公告)号：US20240273241A1

公开(公告)日：2024-08-15

申请号：US18642370

申请日：2024-04-22

Applicant: Alibaba Group Holding Limited

Inventor： Xiaoxia CUI ,  Xuanle REN

IPC: G06F21/74 ,  G06F1/26 ,  G06F15/78 ,  G06F21/60 ,  H04L9/08

CPC classification number: G06F21/74 ,  G06F1/26 ,  G06F21/602 ,  H04L9/08 ,  G06F15/7807 ,  G06F2221/2149

Abstract: A processing unit includes a processor that is adapted to start a secure monitor and establish and set one or more of a crypto enclave and a runtime enclave. The processor is further adapted to establish a plurality of application enclaves and set each of the plurality of application enclaves. The processor is furthermore adapted to and check a to-be-started application program to ensure that the application program can be run securely.

公开(公告)号：US20240195605A1

公开(公告)日：2024-06-13

申请号：US18542308

申请日：2023-12-15

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat

IPC: H04L9/08 ,  B25J15/00 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F9/28 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/445 ,  G06F9/448 ,  G06F9/48 ,  G06F9/50 ,  G06F11/34 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/1045 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/78 ,  G06F16/11 ,  G06F16/22 ,  G06F16/23 ,  G06F16/2453 ,  G06F16/2455 ,  G06F16/248 ,  G06F16/25 ,  G06F16/901 ,  G06F21/10 ,  G06F30/34 ,  G06N3/063 ,  G06Q10/0631 ,  G06Q30/0283 ,  G11C8/12 ,  G11C29/02 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  H04L9/40 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L41/0893 ,  H04L41/0896 ,  H04L41/14 ,  H04L41/5019 ,  H04L41/5025 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/00 ,  H04L49/351 ,  H04L49/40 ,  H04L49/9005 ,  H04L67/1001 ,  H04L67/1008 ,  H04L69/12 ,  H04L69/22 ,  H04L69/32 ,  H04L69/321 ,  H05K7/14 ,  H05K7/18 ,  H05K7/20

CPC classification number: H04L9/0819 ,  B25J15/0014 ,  G06F1/183 ,  G06F1/20 ,  G06F3/0604 ,  G06F3/0605 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/0632 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0683 ,  G06F3/0685 ,  G06F9/28 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/445 ,  G06F9/4494 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5088 ,  G06F11/3442 ,  G06F12/023 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/14 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F15/161 ,  G06F15/17331 ,  G06F15/7807 ,  G06F15/7867 ,  G06F16/119 ,  G06F16/221 ,  G06F16/2237 ,  G06F16/2255 ,  G06F16/2282 ,  G06F16/2365 ,  G06F16/2453 ,  G06F16/2455 ,  G06F16/24553 ,  G06F16/248 ,  G06F16/25 ,  G06F16/9014 ,  G06F30/34 ,  G11C8/12 ,  G11C29/028 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  H04L9/0894 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L41/0893 ,  H04L41/0896 ,  H04L41/5025 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/30 ,  H04L49/351 ,  H04L49/9005 ,  H04L67/1001 ,  H04L67/1008 ,  H04L69/12 ,  H04L69/22 ,  H04L69/32 ,  H04L69/321 ,  H05K7/1489 ,  H05K7/18 ,  H05K7/20209 ,  H05K7/20736 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4856 ,  G06F9/5061 ,  G06F12/0802 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/4022 ,  G06F15/1735 ,  G06F21/105 ,  G06F2200/201 ,  G06F2201/85 ,  G06F2209/509 ,  G06F2212/1044 ,  G06F2212/1052 ,  G06F2212/601 ,  G06F2213/0026 ,  G06F2213/0064 ,  G06F2213/3808 ,  G06N3/063 ,  G06Q10/0631 ,  G06Q30/0283 ,  H04L41/14 ,  H04L41/5019 ,  H04L49/40 ,  H04L63/0428 ,  H05K7/1498

Abstract: Technologies for dynamic accelerator selection include a compute sled. The compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. The compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. The compute engine is also to determine whether to accelerate a function managed by the compute sled. The compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. Also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.

公开(公告)号：US11995463B2

公开(公告)日：2024-05-28

申请号：US17237752

申请日：2021-04-22

Applicant: Marvell Asia Pte, Ltd.

Inventor： Avinash Sodani ,  Senad Durakovic ,  Gopal Nalamalapu

IPC: G06F9/48 ,  G06F3/06 ,  G06F9/52 ,  G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06N5/04

CPC classification number: G06F9/4818 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/4881 ,  G06F9/52 ,  G06N20/00 ,  G06F9/30018 ,  G06F9/30087 ,  G06F9/3869 ,  G06F9/3871 ,  G06F9/522 ,  G06F15/7807 ,  G06F15/7846 ,  G06F15/8053 ,  G06F17/16 ,  G06N5/04

Abstract: A system to support a machine learning (ML) operation comprises an array-based inference engine comprising a plurality of processing tiles each comprising at least one or more of an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform one or more computation tasks on the data in the OCM by executing a set of task instructions. The system also comprises a data streaming engine configured to stream data between a memory and the OCMs and an instruction streaming engine configured to distribute said set of task instructions to the corresponding processing tiles to control their operations and to synchronize said set of task instructions to be executed by each processing tile, respectively, to wait current certain task at each processing tile to finish before starting a new one.

公开(公告)号：US11943347B2

公开(公告)日：2024-03-26

申请号：US16808167

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Or Elnekaveh ,  Ofir Alon ,  Shlomi Agmon

IPC: H04L9/08 ,  G06F15/78 ,  G06F21/44 ,  G06F21/86 ,  H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0869 ,  G06F15/7807 ,  G06F21/44 ,  G06F21/86 ,  H04L9/0662 ,  H04L9/0819 ,  H04L9/3247 ,  G06F2221/2129

Abstract: In an aspect, an integrated tamper resistant device generates initial network credentials for accessing a network, wherein the initial network credentials enable the integrated tamper resistant device to be authenticated by a network solution provider before operational network credentials are provided securely by the network solution provider. The integrated tamper resistant device encrypts the initial network credentials and cryptographically signs the encrypted initial network credentials. The integrated tamper resistant device outputs the encrypted and signed initial network credentials for delivery to the network solution provider.

公开(公告)号：US11934863B2

公开(公告)日：2024-03-19

申请号：US17237752

申请日：2021-04-22

Applicant: Marvell Asia Pte, Ltd.

Inventor： Avinash Sodani ,  Senad Durakovic ,  Gopal Nalamalapu

IPC: G06F9/48 ,  G06F3/06 ,  G06F9/52 ,  G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06N5/04

CPC classification number: G06F9/4818 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/4881 ,  G06F9/52 ,  G06N20/00 ,  G06F9/30018 ,  G06F9/30087 ,  G06F9/3869 ,  G06F9/3871 ,  G06F9/522 ,  G06F15/7807 ,  G06F15/7846 ,  G06F15/8053 ,  G06F17/16 ,  G06N5/04

Abstract: A system to support a machine learning (ML) operation comprises an array-based inference engine comprising a plurality of processing tiles each comprising at least one or more of an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform one or more computation tasks on the data in the OCM by executing a set of task instructions. The system also comprises a data streaming engine configured to stream data between a memory and the OCMs and an instruction streaming engine configured to distribute said set of task instructions to the corresponding processing tiles to control their operations and to synchronize said set of task instructions to be executed by each processing tile, respectively, to wait current certain task at each processing tile to finish before starting a new one.

公开(公告)号：US20240078206A1

公开(公告)日：2024-03-07

申请号：US18502165

申请日：2023-11-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera BALASUBRAMANIAN ,  Joseph ZBICIAK ,  Sureshkumar GOVINDARAJ

IPC: G06F13/42 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/78

CPC classification number: G06F13/42 ,  G06F9/30145 ,  G06F9/3802 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/7807 ,  H04N19/423

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

公开(公告)号：US11892969B2

公开(公告)日：2024-02-06

申请号：US17556755

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Kirk Pfaender

IPC: G06F15/78 ,  G06F1/18 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401

CPC classification number: G06F15/7807 ,  G06F1/189 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/266 ,  G06F9/4403 ,  G06F9/4405 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

公开(公告)号：US20230421358A1

公开(公告)日：2023-12-28

申请号：US18238096

申请日：2023-08-25

Applicant: Intel Corporation

Inventor： Anjaneya Reddy CHAGAM REDDY

IPC: H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/02 ,  H04L41/0896 ,  G06F30/34 ,  B25J15/00 ,  G06F1/18 ,  G06F1/20 ,  G06F11/34 ,  G06F15/78 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/14 ,  H05K7/18 ,  H05K7/20 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/00 ,  H04L49/351 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11

CPC classification number: H04L9/0819 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0659 ,  G06F3/0604 ,  G06F9/5044 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  G06F9/5088 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/028 ,  H04L41/0896 ,  G06F3/0605 ,  G06F30/34 ,  B25J15/0014 ,  G06F1/183 ,  G06F1/20 ,  G06F9/505 ,  G06F11/3442 ,  G06F15/7807 ,  G06F15/7867 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/1489 ,  H05K7/18 ,  H05K7/20209 ,  H05K7/20736 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/221 ,  G06F16/2237 ,  G06F16/24553 ,  G06F16/2282 ,  G06F12/023 ,  G06F12/14 ,  G06F13/1663 ,  G06F15/17331 ,  G06F3/0611 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F3/0613 ,  G06F3/0629 ,  G06F9/4494 ,  G06F9/28 ,  G06F15/161 ,  G06F3/0644 ,  G06F3/0683 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/30 ,  H04L49/351 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/445 ,  G06F3/0632 ,  G06F3/065 ,  G06F3/0685 ,  G06F3/0673 ,  G06F12/0607 ,  G06F16/2455 ,  G06F16/2365 ,  G06F16/248 ,  G06F16/2255 ,  G06F16/9014 ,  G06F16/119 ,  G06F3/0647 ,  G06F12/06 ,  H04L9/0894 ,  G06F2209/509 ,  G06F9/4401 ,  G06F9/44

Abstract: Technologies for allocating resources across data centers include a compute device to obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload. The compute device is also to determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data. Additionally, the compute device is to allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node. The supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located. Other embodiments are also described and claimed.

公开(公告)号：US20230418764A1

公开(公告)日：2023-12-28

申请号：US18460772

申请日：2023-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F9/345 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F9/30065 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30149 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/48 ,  G06F17/16 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/3887 ,  H03H17/0664 ,  G06F9/3856 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/3802 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F11/10 ,  G06F9/3822 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/30145

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.