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公开(公告)号：US20150154731A1
公开(公告)日：2015-06-04
申请号：US14614967
申请日：2015-02-05
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
CPC classification number: G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
Abstract translation: 在一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且通过处理器对顶点数据执行顶点操作，除非通用寄存器块在其中没有足够的可用空间 存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令由处理器执行或正在执行的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。
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公开(公告)号：US20140292784A1
公开(公告)日：2014-10-02
申请号：US14299600
申请日：2014-06-09
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US20130215128A1
公开(公告)日：2013-08-22
申请号：US13846210
申请日：2013-03-18
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US11605149B2
公开(公告)日：2023-03-14
申请号：US17708500
申请日：2022-03-30
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20200043127A1
公开(公告)日：2020-02-06
申请号：US16601260
申请日：2019-10-14
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew F. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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Patent Agency Ranking
公开(公告)号：US10346945B2
公开(公告)日：2019-07-09
申请号：US15901603
申请日：2018-02-21
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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公开(公告)号：US08749563B2
公开(公告)日：2014-06-10
申请号：US13846210
申请日：2013-03-18
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
CPC classification number: G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。
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公开(公告)号：US11361399B2
公开(公告)日：2022-06-14
申请号：US17167717
申请日：2021-02-04
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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公开(公告)号：US11328382B2
公开(公告)日：2022-05-10
申请号：US17230129
申请日：2021-04-14
Applicant: ATI Technologies ULC
Inventor： Stephen L. Morein , Laurent Lefebvre , Andrew E. Gruber , Andi Skende
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20210158473A1
公开(公告)日：2021-05-27
申请号：US17167717
申请日：2021-02-04
Applicant: ATI Technologies ULC
Inventor： Laurent Lefebvre , Andrew Gruber , Stephen Morein
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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