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    Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements
    31.
    发明申请
    Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements 有权
    用于确定对输入数据元素执行数据处理操作的处理路径的数据处理装置和方法

    公开(公告)号：US20050210095A1

    公开(公告)日：2005-09-22

    申请号：US10803164

    申请日：2004-03-18

    申请人： David Lutz ,  Christopher Hinds

    发明人： David Lutz ,  Christopher Hinds

    IPC分类号： G06F7/02 ,  G06F7/38 ,  G06F7/485 ,  G06F7/499

    CPC分类号： G06F7/485 ,  G06F7/02 ,  G06F7/49936

    摘要： The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists. Further, at least one detector logic unit is provided which is operable to receive both the first exponent and the second exponent and to detect the presence of the predetermined alignment condition. Each detector logic unit comprises half adder logic operable to perform a half adder operation to logically subtract one of the first and second exponents from the other of the first and second exponents to produce at least a sum data value of sum and carry data values representing the result of the half adder operation. Further, each detector logic unit comprises generation logic operable to receive the sum data value and to generate a select signal which is set if the sum data value has a predetermined value indicating the existence of the predetermined alignment condition. The processing logic is then operable to select the first data processing path to perform the data processing operation if the select signal from one of the at least one detector logic units is set. The particular structure of detector logic unit provided enables a fast detection of the existence of the predetermined alignment condition, which enables an early selection of the first data processing path if the select signal is set. This enables significant power and area savings to be made.

    摘要翻译： 本发明提供一种用于对第一和第二浮点数据元素执行数据处理操作的数据处理装置和方法，所述第一浮点数据元素指定第一指数，所述第二浮点数据元素指定第二指数。 数据处理装置包括处理逻辑，其提供可选择执行数据处理操作的多个处理路径，包括可操作以在存在预定对准条件时执行数据处理操作的第一处理路径。 此外，提供至少一个检测器逻辑单元，其可操作以接收第一指数和第二指数，并检测预定对准条件的存在。 每个检测器逻辑单元包括半加法器逻辑，可操作以执行半加法器操作以逻辑地从第一和第二指数中的另一个指数中减去第一和第二指数之一，以产生和的和数据值和携带数据值， 半加法器操作的结果。 此外，每个检测器逻辑单元包括生成逻辑，其可操作以接收和数据值，并且如果和数据值具有指示存在预定对准条件的预定值，则生成选择信号。 如果设置了来自至少一个检测器逻辑单元之一的选择信号，则处理逻辑然后可操作以选择第一数据处理路径来执行数据处理操作。 提供的检测器逻辑单元的特定结构使得能够快速检测预定对准条件的存在，如果设置了选择信号，则能够早期选择第一数据处理路径。 这样可以实现显着的功率和面积节省。

    Data processing apparatus and method for comparing floating point operands
    32.
    发明申请
    Data processing apparatus and method for comparing floating point operands 有权

    公开(公告)号：US20050210093A1

    公开(公告)日：2005-09-22

    申请号：US10805502

    申请日：2004-03-22

    申请人： Christopher Hinds ,  David Lutz

    发明人： Christopher Hinds ,  David Lutz

    IPC分类号： G06F7/02 ,  G06F7/42 ,  G06F7/483

    CPC分类号： G06F7/026 ,  G06F7/483

    摘要： The present invention provides a data processing apparatus and method for comparing first and second floating point operands to produce a comparison result. Each floating point operand has a sign component, an exponent component, and a fraction component. The data processing apparatus comprises first processing logic operable to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, the predetermined number being less than the total number of bits constituting the fraction component. The first processing logic is further operable to receive the sign components and the exponent components of the first and second floating point operands and to compare the sign components, the exponent components and the first components of the first and second floating point operands in order to produce a plurality of signals indicative of the comparison. Evaluation logic is then used to evaluate whether the comparison result can be determined from those plurality of signals, and if so, the comparison result is determined. Further, second processing logic is provided which is operable, in the event that the evaluation logic determines that the comparison result cannot be determined from the plurality of signals, to receive, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than the predetermined number of most significant bits. The second processing logic then compares the second components of the first and second floating point operands in order to produce at least one further signal indicative of the comparison, and the evaluation logic is further operable to determine the comparison result from the plurality of signals and the at least one further signal. This technique provides a particularly quick and power efficient technique for producing the comparison result.

    Auxiliary conveyor with adjustable trays
    33.
    发明申请
    Auxiliary conveyor with adjustable trays 失效
    带可调托盘的辅助输送机

    公开(公告)号：US20050115809A1

    公开(公告)日：2005-06-02

    申请号：US10874688

    申请日：2004-06-23

    申请人： David Lutz

    发明人： David Lutz

    IPC分类号： B65G1/02 ,  B65G13/12 ,  B65G13/00

    CPC分类号： B65G1/023 ,  B62B2203/74 ,  B65G13/12

    摘要： A conveyor includes a frame having a plurality of upstanding legs. At least one tray unit is carried on the frame. The tray unit includes at least one connector element. The conveyor further includes at least one clip connectable to the frame and having at least one attachment element configured to releasably engage the connector element of the tray. The connector elements can be spaced holes located along the sides of the tray unit. The attachment element can be a projection or tooth on the tray clip configured to selectively engage one or more of the holes on the side of the tray unit. The clip can include a locking arm to lock the tray to the clip to prevent the tray from sliding during use. The width of the frame and/or the tray unit can be adjusted.

    摘要翻译： 输送机包括具有多个直立腿的框架。 框架上至少装有一个托盘单元。 托盘单元包括至少一个连接器元件。 输送机还包括至少一个可连接到框架的夹子，并具有构造成可释放地接合托盘的连接器元件的至少一个附接元件。 连接器元件可以是沿着托盘单元的侧面设置的间隔开的孔。 附接元件可以是托盘夹上的突出物或齿，其构造成选择性地接合托盘单元侧上的一个或多个孔。 夹子可以包括锁定臂以将托盘锁定到夹子以防止托盘在使用期间滑动。 可以调节框架和/或托盘单元的宽度。

    Self testing digital fault interrupter
    38.
    发明授权
    Self testing digital fault interrupter 有权
    自检数字故障断路器

    公开(公告)号：US07149065B2

    公开(公告)日：2006-12-12

    申请号：US10461874

    申请日：2003-06-16

    申请人： John R. Baldwin ,  Nelson Bonilla ,  Joseph DeBartolo, Jr. ,  David Lutz ,  Sorin I. Mortun ,  Daming Yu

    发明人： John R. Baldwin ,  Nelson Bonilla ,  Joseph DeBartolo, Jr. ,  David Lutz ,  Sorin I. Mortun ,  Daming Yu

    IPC分类号： H02H3/16

    CPC分类号： H01H83/04 ,  H02H3/04 ,  H02H3/335

    摘要： A fault interrupter apparatus having a line side and a load side and a conductive path there between. The apparatus includes a solenoid that is adapted to move a plurality of contacts disposed in the conductive path from a first position to a second position, an alarm indicator that is adapted to provide status information on the operation of the fault interrupter apparatus, and a processor that is adapted to detect four condition states of the fault interrupter and indicate the four condition states of the fault interrupter using the alarm indicator.

    摘要翻译： 一种具有线路侧和负载侧以及其间的导电路径的故障断续器装置。 该装置包括螺线管，其适于将布置在导电路径中的多个触点从第一位置移动到第二位置;报警指示器，其适于提供关于故障中断装置的操作的状态信息;以及处理器 适用于检测故障中断器的四种状态，并使用报警指示器指示故障中断器的四种状态。

    Data processing apparatus and method for performing floating point addition
    39.
    发明申请
    Data processing apparatus and method for performing floating point addition 有权
    用于执行浮点加法的数据处理装置和方法

    公开(公告)号：US20060206556A1

    公开(公告)日：2006-09-14

    申请号：US11078699

    申请日：2005-03-14

    申请人： David Lutz ,  Christopher Hinds

    发明人： David Lutz ,  Christopher Hinds

    IPC分类号： G06F7/50

    CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49963 ,  G06F2207/3884

    摘要： A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic. If the addition is a like-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective 1-bit right shift to normalise the sum value, whereas if the addition is an unlike-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective 1-bit left shift to normalise the sum value.

    摘要翻译： 提供了一种数据处理装置和方法，用于添加第一和第二浮点操作数的n位有效值以产生n位结果。 数据处理装置包括用于确定第一和第二浮点操作数中的哪一个是较大操作数的确定逻辑。 如果存在预定标准，则使用第一加法器逻辑来执行第一和第二浮点操作数的n比特有效值的相加以产生和值，同时使用第二加法器逻辑，如果不存在预定标准， 执行该添加。 然后，结果逻辑可以从第一加法器逻辑的输出或第二加法器逻辑的输出导出n位结果。 如果加法是类似签名的加法，则对于由第一加法器逻辑产生的和值将要求有效的1位右移以标准化和值的一组情况，确定预定标准存在，而如果 另外是一个不同签名的加法，对于由第一加法器逻辑产生的和值将要求至少一个有效的1位左移以归一化和值的情况，确定预定准则存在。