公开(公告)号：US20070146013A1

公开(公告)日：2007-06-28

申请号：US11321328

申请日：2005-12-28

申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： H03K19/094

CPC分类号： H03K19/0963 ,  G01R31/3008 ,  G01R31/31721 ,  H03K19/00361 ,  H03K19/00384

摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

摘要翻译： 这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。 在一些实施例中，可编程保持器电路耦合到寄存器文件电路。 包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。 控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。 要求保护或以其他方式公开其他实施例。

公开(公告)号：US07196548B2

公开(公告)日：2007-03-27

申请号：US10927574

申请日：2004-08-25

申请人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： H03K19/094 ,  H03K17/16

CPC分类号： H03K3/356156 ,  H03K3/356191

摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

公开(公告)号：US07099219B2

公开(公告)日：2006-08-29

申请号：US11018012

申请日：2004-12-20

申请人： Steven K. Hsu ,  Atul Maheshwari ,  Ram K. Krishnamurthy

发明人： Steven K. Hsu ,  Atul Maheshwari ,  Ram K. Krishnamurthy

IPC分类号： G11C7/02 ,  G11C11/00 ,  G11C11/34 ,  G11C8/00

CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C11/56

摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

摘要翻译： 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。

公开(公告)号：US20060133183A1

公开(公告)日：2006-06-22

申请号：US11018012

申请日：2004-12-20

申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C11/56

摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

摘要翻译： 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。