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    Dynamic logic with adaptive keeper
    1.
    发明申请
    Dynamic logic with adaptive keeper 有权
    动态逻辑与自适应守门员

    公开(公告)号：US20070146013A1

    公开(公告)日：2007-06-28

    申请号：US11321328

    申请日：2005-12-28

    申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

    发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

    IPC分类号： H03K19/094

    CPC分类号： H03K19/0963 ,  G01R31/3008 ,  G01R31/31721 ,  H03K19/00361 ,  H03K19/00384

    摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.

    摘要翻译： 这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。 在一些实施例中，可编程保持器电路耦合到寄存器文件电路。 包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。 控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。 要求保护或以其他方式公开其他实施例。

    MULTI READ PORT BIT LINE
    2.
    发明申请
    MULTI READ PORT BIT LINE 有权
    多读端口位线

    公开(公告)号：US20060133183A1

    公开(公告)日：2006-06-22

    申请号：US11018012

    申请日：2004-12-20

    申请人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

    发明人： Steven Hsu ,  Atul Maheshwari ,  Ram Krishnamurthy

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C11/56

    摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.

    摘要翻译： 在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。 位线有阻抗。 位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。 在此描述或以其他方式要求保护的其它实施例。

    Data converter and a delay threshold comparator
    4.
    发明授权
    Data converter and a delay threshold comparator 失效
    数据转换器和延迟阈值比较器

    公开(公告)号：US07603398B2

    公开(公告)日：2009-10-13

    申请号：US11094811

    申请日：2005-03-31

    申请人： Atul Maheshwari ,  Sanu K. Matthew ,  Mark A. Anders ,  Ram Krishnamurthy

    发明人： Atul Maheshwari ,  Sanu K. Matthew ,  Mark A. Anders ,  Ram Krishnamurthy

    IPC分类号： G06F7/00 ,  G06F15/00

    CPC分类号： G06F9/3869 ,  G06F7/74

    摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

    摘要翻译： 对于一个公开的实施例，转换器将2N位数据转换成指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。

    Single ended current-sensed bus with novel static power free receiver circuit
    5.
    发明授权
    Single ended current-sensed bus with novel static power free receiver circuit 失效
    单端电流检测总线，具有新颖的静态无功接收电路

    公开(公告)号：US07196548B2

    公开(公告)日：2007-03-27

    申请号：US10927574

    申请日：2004-08-25

    申请人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

    发明人： Mark A. Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

    IPC分类号： H03K19/094 ,  H03K17/16

    CPC分类号： H03K3/356156 ,  H03K3/356191

    摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

    摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

    Single ended current-sensed bus with novel static power free receiver circuit
    6.
    发明申请
    Single ended current-sensed bus with novel static power free receiver circuit 失效
    单端电流检测总线，具有新颖的静态无功接收电路

    公开(公告)号：US20060044017A1

    公开(公告)日：2006-03-02

    申请号：US10927574

    申请日：2004-08-25

    申请人： Mark Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Atul Maheshwari ,  Ram Krishnamurthy

    IPC分类号： H03K19/096

    CPC分类号： H03K3/356156 ,  H03K3/356191

    摘要： A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.

    摘要翻译： 本文描述了具有新颖的静态无功接收器电路的单端电流感测总线。 在一个实施例中，接收器电路示例包括锁存电路，以在响应于输入的评估阶段期间锁存第一输出和第二输出的值;耦合到锁存电路的预充电电路以预充电锁存电路 以及耦合到预充电电路和锁存电路的静态功耗阻塞（SPDB）电路，以在预充电阶段期间基本上阻止静态功率消散。 还描述了其它方法和装置。

    Data converter and a delay threshold comparator
    7.
    发明申请
    Data converter and a delay threshold comparator 失效
    数据转换器和延迟阈值比较器

    公开(公告)号：US20060221724A1

    公开(公告)日：2006-10-05

    申请号：US11094811

    申请日：2005-03-31

    申请人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    发明人： Atul Maheshwari ,  Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy

    IPC分类号： G11C7/06

    CPC分类号： G06F9/3869 ,  G06F7/74

    摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.

    摘要翻译： 对于一个所公开的实施例，转换器将2个N位数据转换为指示具有预定逻辑值的数据中的位数的N位值。 转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。 基于比较器的输出产生N位值。 对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号 值。 比较器然后基于延迟信号产生位值。

    Low-noise leakage-tolerant register file technique
    8.
    发明申请
    Low-noise leakage-tolerant register file technique 有权
    低噪声容错寄存器文件技术

    公开(公告)号：US20060013035A1

    公开(公告)日：2006-01-19

    申请号：US10879090

    申请日：2004-06-30

    申请人： Steven Hsu ,  Ram Krishnamurthy

    发明人： Steven Hsu ,  Ram Krishnamurthy

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

    摘要翻译： 存储器电路包括字线，包括一个或多个存储器单元或子单元的数据存储电路，以及耦合在字线和N个存储单元之间的反相器。 逆变器将输入到单元或子单元的读取端口的字线信号反相。 由于字线逆变器对于每个单元或子单元是局部的，所以DC偏移显着减小，这转化为泄漏电流的减小。

    Register file with a selectable keeper circuit
    9.
    发明申请
    Register file with a selectable keeper circuit 有权
    使用可选保持电路注册文件

    公开(公告)号：US20050068814A1

    公开(公告)日：2005-03-31

    申请号：US10676276

    申请日：2003-09-30

    申请人： Bhaskar Chatterjee ,  Steven Hsu ,  Ram Krishnamurthy

    发明人： Bhaskar Chatterjee ,  Steven Hsu ,  Ram Krishnamurthy

    IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C29/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C2207/104

    摘要： A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.

    摘要翻译： 寄存器文件包括多电平多路复用器输出电路，其耦合到耦合到所述全局位线跟踪和驱动信号迹线的全局位跟踪和保持器电路。 寄存器文件还具有耦合到所述保持器电路的解码器电路，以选择性地将驱动信号迹线与所述全局位线分离。

    RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD
    10.
    发明申请
    RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD 审中-公开
    用于在数据字中记录数据的可重新配置的设备

    公开(公告)号：US20140013082A1

    公开(公告)日：2014-01-09

    申请号：US13976923

    申请日：2011-12-30

    申请人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    发明人： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30036

    摘要： Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements.

    摘要翻译： 公开了一种用于数据操作的系统和设备及相关方法，特别是用于SIMD操作，例如置换，移位和旋转。 一种装置包括：重新定位子字边界上的数据的置换部分和重新定位小于子字宽度的数据距离的移位部分。 子字宽度是可配置和可选择的，并且置换部分和移位部分可以在不同的边界宽度上操作。 在第一阶段中，置换部分将数据重新定位在最近的子字边界处，并且在第二阶段中，移位部分将数据重新定位到其最终期望的位置。 移位部分包括以对数级联关系设置的多级。 另外，每个多级中的每个移位器是高度连接的，允许快速和精确的数据移动。