公开(公告)号：US20230034707A1

公开(公告)日：2023-02-02

申请号：US17962408

申请日：2022-10-07

Applicant: BFLY OPERATIONS, INC.

Inventor： Jianwei Liu ,  Keith G. Fife

IPC: B81B7/00 ,  B06B1/02 ,  B81C1/00

Abstract: A method of manufacturing an ultrasound imaging device involves forming an interposer structure, including forming a first metal material within openings through a substate and on top and bottom surfaces of the substrate, patterning the first metal material, forming a dielectric layer over the patterned first metal material, forming openings within the dielectric layer to expose portions of the patterned first metal material, filling the openings with a second metal material, forming a third metal material on the top and bottom surfaces of the substrate, and patterning the third metal material. The method further involves forming a packaging structure for an ultrasound-on-chip device, including attaching a multi-layer flex substrate to a carrier wafer, bonding a first side of an ultrasound-on-chip device to the multi-layer flex substrate, bonding a second side of the ultrasound-on-chip device to a first side of the interposer structure, and removing the carrier wafer.

公开(公告)号：US11484911B2

公开(公告)日：2022-11-01

申请号：US16844857

申请日：2020-04-09

Applicant: BFLY Operations, Inc.

Inventor： Lingyun Miao ,  Jianwei Liu

IPC: B06B1/00 ,  B06B1/02 ,  B81B3/00 ,  B81C1/00

Abstract: A ultrasonic transducer device includes a transducer bottom electrode layer disposed over a substrate, and a plurality of vias that electrically connect the bottom electrode layer with the substrate, wherein substantially an entirety of the plurality of vias are disposed directly below a footprint of a transducer cavity. Alternatively, the transducer bottom electrode layer includes a first metal layer in contact with the plurality of vias and a second metal layer formed on the first metal layer, the first metal layer including a same material as the plurality of vias.

公开(公告)号：US11426143B2

公开(公告)日：2022-08-30

申请号：US17088336

申请日：2020-11-03

Applicant: BFLY Operations, Inc.

Inventor： Keith G. Fife ,  Jianwei Liu

IPC: H01L29/84 ,  A61B8/00 ,  H01L41/293 ,  H01L41/113

Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.